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The paper investigates the use of the existing CAD framework for digital circuit synthesis to design and synthesize a select set of mixed-signal functions like analog-to-digital and digital-to-analog conversions. This approach leads to fast and low cost design of technology portable system-on-chip solutions with analog interfaces. Some circuit examples for implementation of data conversion using digital...
This work proposes a new method of synthesizingasynchronous circuits targeting its practical usability. The keycontribution of this work is finding an effective technique ofinter-mixing the two design principles namely handshaking basedsingle-rail and timing annotated (i.e., delay insensitive) dual-railof asynchronous circuits. Precisely, we propose clever ways ofpartitioning an input (synchronous)...
In this work, an InSb/Si heterojunction hetero gatedielectric double gate TFET (HTFET) having a split pocket atSource-Channel junction has been designed and its analog/RFperformance has been investigated. The analog/RF performanceof the device is analysed in terms of I-V characteristics, transcon-suctance (gm), parasitic capacitances, cut-off frequency (fT) andgain bandwidth product (GBW). Maximum...
Stochastic computing (SC) encodes data in the signal probabilities associated with pseudo-random bit-streams. It enables very low-area and low-power arithmetic operations using standard VLSI circuits, it is also highly error-tolerant. While addition, subtraction and multiplication have extremely simple SC implementations, this is not true for division. Known stochastic dividers employ sequential logic...
This paper proposes the design of an adaptive filterin stochastic circuits. The proposed circuit requires lower areaand power than a conventional stochastic implementation. In theproposed design, the stochastic multiplier is implemented by anXNOR gate, as in a conventional scheme. However, the stochasticadder based on a multiplexer is not a very efficient implementationdue to the three required stochastic...
Physical unclonable functions (PUF) are a promising approach in design for trust and security. A PUF derives a unique identifier for different similar dies using some of their physical characteristics, so it can be used to authenticate chips and to fight against counterfeiting and theft of devices. The transient effect ring oscillator (TERO) PUF is based on the extraction of the entropy of the process...
In this paper, we analyze the impact of voltage, temperature and body-biasing on the detection of resistive short defects for low-VT (LVT) and regular-VT (RVT) configurations of a 28nm UTBB FDSOI (Ultra Thin Body & BOX Fully Depleted Silicon-On-Insulator) technology. We implemented a similar design in each configuration and compared their electrical behaviors with the same resistive short...
The globalization of Integrated Circuits (ICs) supply chain has raised security concerns on how to ensure the integrity and the trustworthiness of fabricated circuits. While existing attack and protection methods are developed for CMOS based circuits, the introduction of emerging transistors acts as a double-sided sword. The usage of emerging devices introduces new security issues which the attackers...
Numerous side-channel attacks on integrated circuitimplementations of cryptographic systems have been demonstrated in literature. Insecure implementations can reveal secret information through data dependencies in dynamic and leakage power profiles. Side-channel resistant logic styles are effective against dynamic power analysis attacks, but are suggested to exhibit weaknesses against the less common...
Power gating (PG) is an effective power efficiency improvement technique. Future general-purpose graphics processing units (GPGPUs) will likely feature hundreds of compute units (CUs) and be power constrained, which leads to serious challenges to existing PG methodologies. In this paper, we propose novel design-time and run-time techniques to effectively implement power gating in future GPGPUs. Based...
The insertion of malicious alterations to a circuit, referred to as Hardware Trojans, is a threat considered more and more seriously during the last years. Numerous methods have been proposed in the literature to detect the presence of such alterations. More recently, Design-for-Hardware-Trust (DfHT) methods have been proposed, that enhance the design of the circuit in order to incorporate features...
With decreasing size of transistors, the impact oftransient faults as well as the local and global variability of transistors increases, affecting system functions and performances. Formal verification may be used to prove that a circuit isrobust against transient and parametric faults. However, a modelincluding timing information combined with extracted electricalparameters is typically too large...
The paper describes a method of verifying sequential arithmetic circuits by adding a special type of redundancy, called "Vanishing Polynomials" and "Don't Care Polynomials". The proof of functional correctness consists in transforming the polynomial expression at the primary outputs into a unique polynomial in the primary inputs and comparing the computed...
Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using...
Research on memristors have drawn wide attentionin recent years as these devices exhibit unique properties whichcan be used to perform various logic and memory operations. Memristor based memory systems are expected to replace flashmemory devices in the near future. In addition, synthesis andoptimization of boolean functions using memristors are becomingan important area of research. There are various...
Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling Vdd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However,...
In this paper, a low power 5-bit hybrid flasharchitecture is proposed. The proposed analog-to-digital con-verter (ADC) uses appropriate combination of both conventionaldouble-tail comparators and standard cell comparators. Stan-dard cell comparators are used to reduce power consumption. Thus, the proposed hybrid architecture results in extendeddynamic range when compared to standard cell and thresholdinverter...
Important characteristic of any VLSI circuit isits power consumption, reliability, operating speed and siliconarea. Dynamic CMOS designs provide high operating speedscompared to static CMOS designs combined with low siliconarea requirements. Pipelines can be used for achieving highcircuit operating speeds. However, as the operating frequencyincreases, the number of pipeline stages should also increaseand...
For 7 series Xilinx FPGAs, this paper shows that it is risky to believe that so fundamental operation as data delay must be always implemented without wasting chip area, even when design tools are not especially guided by a developer. Against this background, two solutions are presented that allow for minimizing the area occupied by flip-flops used to delay data that comes from outside the slices...
This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. This new architecture does not require fine-grained location of fault, and the error map is stored in non-volatile memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the...
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