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This paper presents an improved technique for the calibration of the relaxation oscillators with respect to the delay of the comparators. The drawbacks of the conventional topology for the relaxation oscillators are analyzed. Based on the analysis, the circuit modification which resolves the effects of the comparator delay in the trimming procedure is proposed. The simulations in ams 0.18μ CMOS technology...
The paper presents a subsampling PLL which uses a 10-bit, 0.5 ps unit step Digital-to-Time Converter (DTC) in the phase-error comparison path for the fractional-N lock. The gain and nonlinearity of the DTC can be digitally calibrated in the background while the PLL operates normally. During fractional multiplication of a 40 MHz reference to frequencies around 10 GHz, the measured jitter is in the...
The lumped models of several capacitors in SMD-0603 package are extracted from S-parameter measurements. The S-parameters of the SMD components are obtained: (i) by modelling the RF connector and transmission lines and de-embedding, and (ii) by directly calibrating the reference plane to the SMD component using on-board calibration standards. The extracted parasitics related to the SMD component package...
The exploration and analysis of large databases represents a subject of research efforts for several industries. In this paper the case of production of flat metals, where advanced optimization technologies based on mathematical modeling are integrated in the automation architecture together with databases, is discussed: in particular the use of MATLAB as an offline tool for model analysis and calibration...
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