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Industry-standard Circuit Reliability simulation Tools (ICRT) to simulate Channel Hot Carrier (CHC) is either not possible at the full-chip level consisting of few million transistors or time consuming and prone to abrupt termination of simulation due to resource usage anomalies at reasonable large sub-block level. We have proposed a hierarchical design-in-reliability methodology to identify CHC aging...
The performance of NAND flash based solid-state drives (SSDs) is highly dependent on the application's read and write characteristics [3], where "intensity" is defined as ratio of read:write requests, and "write- hot/cold" considers the write frequency. Moreover, NAND flash memory's reliability degrades with write/erase (W/E) cycling. To optimize performance and reliability, conventional...
Highly reliable LDPC ECC is introduced to improve the reliability of solid-state drives (SSDs). Although conventional AEP-LDPC ECC [3] is 12x highly reliable than BCH ECC, its error-correction capability is degraded due to the burst-errors and inaccurate log- likelihood ratio (LLR). To improve the reliability of TLC NAND flash, this paper proposes the burst-error masking (BEM) and program-disturb...
The effect of read disturb on partially programmed blocks of MLC NAND is evaluated using experimental data from 2y-, 1y- and 1x-nm Flash memory devices. We demonstrate that when a partially programmed block is exposed to a large number of reads before it is finalized in terms of page programming, the remaining pages will exhibit a significant bit error-rate (BER) increase. The page-BER is characterized...
The Resistive RAM (RRAM) technology is emerging as one of the possible candidates in replacing state-of-the-art NAND Flash for Solid State Drives (SSDs) applications. However, the RRAM architectures developed so far evidence a granularity mismatch between their page size and the typical host application payloads, forcing the use of multi-plane approaches to mimic NAND Flash thus affecting the figures...
We look at the challenges for scaling planar NAND flash for sub-15nm nodes, and show the implementation of hybrid poly\metal floating gate (FG), HfAlO based IGD, junctionless array, WL trimming, and EUV spacer defined double patterning in a fully planar NAND Flash array with good programming performance
The privacy-protection solid-state storage (PP-SSS) system is a proposal for Internet-data's "right to be forgotten", in which data-lifetimes are specified without file-system overhead. In NAND flash memory, the data-lifetimes are controlled by intentionally injecting errors into the data during write, to accelerate retention failure. However, the previously reported PP-SSS [1] has 2 issues,...
NAND Flash memory became a standard semiconductor nonvolatile memory. Everyone in the world has widely used NAND Flash memory in many applications, such as digital camera, USB drive, portable music player, smartphone, and tablet-PC. The cloud data server started to use SSD (Solid State Drive) which was based on NAND Flash memory. Recently, 3-dimensional (3D) NAND flash memory was developed and started...
In this paper, we investigate the effect of High Pressure Hydrogen or Deuterium Annealing on a vertical charge trapping NAND memory device. Strong improvement is obtained in Vt, subthreshold slope and drive current of the transistors by a better passivation of charge by either species in the bulk ONO memory stack, at the interface between ONO and Poly-Si channel, and in the bulk Poly-Si. Program /...
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