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Analog circuit sizing has become a very challenging process due to increased non-idealities for advanced technology nodes. Moreover, reliability of circuits has become a major concern, where process variations and aging phenomena have been substantially worsened in deep-sub-micron devices. Thereby, traditional circuit optimization tools have been replaced by more complicated ones, which take reliability...
Reliability has become a critical challenge in integrated circuit design in today's CMOS technologies. Aging problems have been added to the well-known issues due to spatial variations that are caused by imperfections in the fabrication process. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers (HC) cause a time-dependent variability that is added...
Negative Bias Temperature Instability (NBTI) is one of the degradation phenomena that reduces the circuit reliability in immensely scaled CMOS technologies. In this work, effects of NBTI have been examined on a single PMOS transistor and further on SRAM operations. It has been observed that read Static Noise Margin (SNM) of the 6T SRAM cell degrades due to NBTI. To compensate this degradation different...
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