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New challenges are arising with the entrance in sub-100 nm CMOS nodes. Dominant sources of the MOSFET leakage which differ from those of previous nodes are examined. Consequences for the analog circuit design due to smaller dimensions and an accompanying higher variance of important analog parameters like threshold voltage in combination with shrinking VDD headroom are highlighted. As an example,...
In this work, a 6-bit 800 MS/s flash analog-to-digital converter (ADC) is proposed. An optimized resistance ratio averaging scheme is applied to: (1) reduce the offset, nonlinearity, (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is...
The aim of this paper is energy dissipation analysis in regards to supply voltage and temperature. The basis of all simulations are 12 different transistors coming from 6 different CMOS technologies (from 180nm to 14nm). Dynamic energy used to switch a gate from one state to the other was evaluated in a range of temperature for different supply voltages. In order to guarantee a realistic timing of...
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