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MOM (Metal-Oxide-Metal) capacitors are today the workhorses for providing a large number of stored charges in sub-100 nm CMOS nodes. In these nodes the BEOL (Back-End-to-Line) distances are in the range of tens of nanometers. Even with increasing BEOL distances in broadly exploited and less expensive CMOS nodes with critical dimensions=130 nm or greater these structures are approaching into the focus...
New challenges are arising with the entrance in sub-100 nm CMOS nodes. Dominant sources of the MOSFET leakage which differ from those of previous nodes are examined. Consequences for the analog circuit design due to smaller dimensions and an accompanying higher variance of important analog parameters like threshold voltage in combination with shrinking VDD headroom are highlighted. As an example,...
Different types of capacitors are reviewed with respect to charge storing in heterogeneous integrated systems. Starting with the commonly used gate oxide capacitors in CMOS technologies, we discuss challenges for thinner oxides. A PSP model is shown to provide a good fit of the gate capacitance vs. the gate voltage for retrograde doping profiles. As an example, a gate capacitor circuitry is discussed...
The temperature dependency of silicided and blocked p-doped polysilicon resistors is examined in a 90 nm CMOS Flash technology. The blocked resistors are modeled in two portions to describe the silicided and the blocked regions separately. A process-control-monitor (PCM) like layout of the resistor test structures makes it possible to measure the resistance either in a lab environment manually or...
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