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Compressors play a significant role in overall performance of multipliers and hence in efficiency of arithmetic circuits. To further improvement of multipliers higher order compressors have been considered. In this paper, two novel 5:2 compressors are presented. The proposed architectures lay emphasis on the idea of making the carry-out signal Cout2 independent of Cin1. Therefore, we have developed...
An analytical model for double-gate (DG) tunnel FETs (TFETs) using two-dimensional (2-D) solution of Poisson's equation is presented. We derived analytical expressions for the drain current and sub-threshold swing from the maximum electric field using the Kane model. The model is validated via comparing it with TCAD simulation results for different sets of parameters. The results show a good agreement...
Speed, power and chip area are the crucial parameters in logic circuit designs. With the gate diffusion input (GDI) technique, low power logic gates can be designed with the minimum number of transistors. In this paper the modified GDI (m-GDI) cell based on the basic GDI cell is proposed for designing the logic circuits in nano process. In the proposed GDI cell, the chip area for the pull up and pull...
The basic element in designing the circuit function single-flux quantum (SFQ) like demultiplexer, frequency dividers and binary counters in integrated circuits is Toggle flip flap (TFF). By using gate diffusion input (GDI) technique in designing the logic gates, power consumption, delay, chip area and connection and parasitic capacitors are decreased. In this paper, first, the modified GDI (m-GDI)...
In this paper a flat supply voltage is produced for low-noise and low-jitter applications. A high gain two-stage amplifier, utilizing the indirect frequency compensation technique, is used to enhance the resolution of BGR loop. Then, the temperature-compensated BGR is used within the LDO loop to adjust the supply voltage around the desired value. A new start-up circuit is proposed to simply provide...
Implementation of logic circuits using Quantum-dot Cellular Automata (QCA) technology due to the proper features, e.g. high device density, fast switching time and extremely low power, is an intense research area. Boolean primitives in QCA circuits are the majority gate and inverter. Recently, evolutionary algorithms, especially Genetic Algorithm (GA), have been used for implementing a given Boolean...
In this paper, the quantum transport of a Germanium based Gate-All-Around NanoWire Transistor, GAANWT is simulated in nanoscale regime. We have implemented a 3D ballistic simulator based on the Non-Equilibrium Green Function, NEGF, formalism within the effective mass approximation and the mode space approach. Due to low effective mass of the Germanium, it is a promising channel material in nanoscale...
In this paper, a new architecture for a low-power highspeed Flash Analog-to-Digital Converter (ADC) is presented. Unlike conventional Full-Flash architecture in which power consumption is increased exponentially with the increase of resolution, in this proposed architecture, power consumption varies approximately linearly with the growth of resolution. In fact, by taking advantage of initial intelligent...
Digitally controlled Oscillators used in All Digital PLL. They are main responsible for range of frequency and power consumption in ADPLL. In the Conventional DCO designs, DCO work in one single band. We recommend in this paper presents a new approach on the design of DCO working in band selective reconfigurable mode with control logics. This design allows using DCO in low-frequency low-power applications...
Computers transform to the smaller, faster and more reliable devices year by year. Accordingly designing more efficient logic gates, as the basic blocks of the VLSI chips, are essential for circuit designers. Since the integration reached to its limits through the conventional technologies mainly the CMOS based VLSI designs the quest for the novel promising technologies was commenced. Memristor is...
In this paper, a novel double gate tunnel field effect transistor (DGTFET) configuration with p+-layer in the channel is proposed and investigated. The proposed structure is a Si-channel DGTFET, which has a p+-layer in the channel connected to the P+ source region in order to achieve improved switching and higher ON-current when compared to a conventional TFET. The simulation results of DGTFET with...
A CMOS voltage reference based on the difference between the gate-source voltages of pMOS and nMOS transistors operating in subthreshold region is presented. Power consumption is optimized by subthreshold design and minimizing the number of passive elements in any circuit branches from supply to the ground. A reference voltage of 912 mV with a temperature coefficient of 68 ppm/°C from −40 °C to 120...
In this article partial products algorithm of serial multipliers is presented and different architectures of these kinds of multipliers such as: Successive Addition, Serial-Parallel and Serial-Serial methods are surveyed. With respect to extension capability of pipeline architecture, this circuit is implemented as 4-bit serial-serial multiplier. Some problems have been found and issues were scrutinized...
High-performance Al0.3Ga0.7N/GaN high electron-mobility transistors (HEMTs) with 1 μm gate length have been simulated. The devices exhibited a transconductance of about 100 ms/mm at VDS = 9 V and a minimum noise figure (NFmin) of 0.79 dB at 10 GHz. Also we inserted a 1 nm AlN layer at the interface of Al0.3Ga0.7N/GaN as spacer layer. The AlN produces a larger conduction band offset (ΔEc), higher polarization...
In this paper we present a fault tolerant full adder cell as well as a fault tolerant serial adder circuit. It is worthwhile that this is the first time that a real fault tolerant full adder cell has been proposed. This is the very same for the fault tolerant serial adder cell. We have also generated a program to assess the fault tolerance. While the other full adder designs seem to be sensitive to...
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