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In this paper, we present first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by direct wafer bonding (DWB) process using InGaAs channels grown on 4-inch Si donor substrates with III–V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated...
A 1T-1R pillar-type “topological-switching RAM” (TRAM) and the data retention of GeTe/Sb2Te3 super-lattice were investigated. Reset voltage of TRAM, 2 V, was 40 % of that of the conventional PCM with Ge2Sb2Te5. From data retention evaluation, the TRAM was found to endure the retention at 260 °C for 18 hours.
We demonstrate a Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate (RMG) technology, which uses only thin TiN layers as workfunction (WF)-setting metals for CMOS integration. The SIGMA stack provides 100× PBTI lifetime improvement via band alignment engineering. Moreover, the SIGMA stack enables 9nm more gate length (Lg) scaling compared to the conventional stack with matched...
A scalable multi-VT enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-VT is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ∼400 mV is realized by adjusting the TiN...
We present major breakthroughs in MTJ design for STT-MRAM applications allowing reliable write for pulse lengths down to 1.5ns, data retention up to 125°C for 10 years and full compatibility with BEOL process up to 400°C for 1 hour. We have successfully integrated the novel structure onto an 8Mbit test chip. We demonstrate writing of every single cell in the array using sub-5ns pulses over a wide...
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various...
We demonstrate high performance (HP) s-SiGe pMOS finFETs with Ion/Ieff of ∼1.05/0.52mA/µm and ∼1.3/0.71mA/µm at Ioff=100nA/µm at VDD=0.8 and 1V, extremely high intrinsic performance and source injection velocity. Compared to earlier work, an optimized process flow and a novel interface passivation scheme, result in ∼30% mobility enhancement and dramatic sub-threshold-swing reduction to 65mV/dec. We...
A successful integration of Via-middle TSV process in DRAM technology with major process issues is introduced. Fast TSV open/short detection and how to trade-off in choice repair scheme is discussed. Process development for TSV volume shrink required to reduce dynamic power for driving TSV. Fast Cu leak monitor method is essential to sustaining good quality and Fab process control.
This paper demonstrates an advanced 1.1um pixel backside illuminated CMOS image sensor with a 3D stacked architecture. The carrier wafer in conventional BSI is replaced by ASIC wafer, which contains a part of periphery circuit and is connected to the sensor wafer through bonding technology. With proper layout design and process improvement, the impact of 3D connection (Through Via, TV) on the sensor...
A new oxidation reaction at ultralow temperature (−30°C) by bombardment of O2 neutral beam can be enhanced at the extremely low activation energy, which can efficiently form a thin oxide film of all transition metal, such as platinum and ruthenium. Meanwhile, a novel neutral beam enhanced chemical etching for transition metals and magnetic materials was proposed without chemical and physical damages...
Fast (10ns) and low voltage (2V) programming of Cu atom switch has been demonstrated in a 1Mb switch array for the first time. A newly developed redox-control buffer of Al0.5Ti0.5Ox leads to extremely steep slope switching of voltage dependent time-to-ON-state (56mV/decade), by eliminating metallic Al residues at the Cu surface. The programmed ON-state shows long lifetimes both under data-retention...
For the first time, different impacts of as-grown and generated defects on nm-sized devices are demonstrated. As-grown hole traps are responsible for WDF, which increases with Vg_op and tw. The generated defects are substantial, but do not contribute to WDF and consequently are not detected by RTN. The non-discharging component follows the same model as that for large devices: the ‘AG’ model. Based...
We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si1−xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low...
The thermal stability Δ is a key parameter of the MRAM technology. It determines the current induced switching behavior as well as the reliability performance of e.g. data retention and read-disturb. Therefore a highly accurate assessment of Δ is mandatory for a successful MRAM technology development. In this paper we present a verification methodology based on the statistical data of a 8Mb test vehicle...
The low frequency noise (LFN) mechanisms of TFETs with different source junction design are experimentally studied for the first time, including the random telegraph signal (RTS) noise. Different from MOSFET, due to the non-local band-to-band tunneling (BTBT) mechanism and small LFN-generating area, both 1/f and 1/f2 LFN dependence can be observed in large TFETs with large device to device variability,...
We demonstrate high performance undoped Ge0.92Sn0.08 quantum well (QW) pMOSFETs with in situ Si2H6 passivation on (001), (011) and (111) orientations. (011) and (111)-oriented Ge0.92Sn0.08 QW pFETs achieve higher on-state current ION and effective hole mobility μeff compared to (001) devices. Ge0.92Sn0.08 (111) QW pFETs demonstrate a record high μeff of 845 cm2V−1s−1 for GeSn p-channel devices (Fig...
For the first time, we propose a new ON current boosting technology for TFETs utilizing an isoelectronic trap (IET), which is formed by introducing electrically inactive impurities. We have demonstrated tunneling current enhancement by 735 times in Si-based diodes and 11 times enhancement in SOI-TFETs owing to non-thermal tunneling component by the Al-N isoelectronic impurity complex. The IET technology...
We utilize eye-diagram measurements of timing jitter to investigate the impact of PBTI in devices subject to DC as well as ring oscillator (RO) and pseudo-random binary sequence (PRBS) stress waveforms. We observe that RO measurements miss the relevant random timing jitter increases which are well captured using PRBS measurements. We also observe that DC, RO, and PRBS stresses all introduce similar...
We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 µA/µm at Ioff = 10 nA/µm at VDD = 0.8 V. The BOTS process results...
This paper presents the superior electron and hole mobility on a single orientation Ge substrate for compact and cost-effective CMOS applications. The different scattering mechanisms of electron and hole mobility are discussed for understanding carrier transport physics. On the basis of this understanding, the highest electron mobility of 437 cm2/Vs and hole mobility of 213 cm2/Vs at Ns=1e13 cm−2...
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