Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
Electromigration (EM) is a growing reliability concern in sub-22nm technology. Design teams must apply guardbands to meet EM lifetime requirements, at the cost of performance and power. However, EM lifetime analysis cannot ignore front-end reliability mechanisms such as bias temperature instability (BTI). Although the gate delay degradation due to BTI can be compensated by adaptive voltage scaling...
We propose a prediction of the worst-case noise area of the supply voltage on the power distribution network (PDN). Previous works focus on the worst-peak droop to sign off PDN. In this work, we (1) study the behavior of circuit delay over the worst-area noise (2) study the worst-case noise area of a lumped PDN model (3) develop an algorithm to generate the worst-case current for eneral PDN cases...
Clock grid is a mainstream clock network methodology for high performance microprocessor and SOC designs. Clock skew, power usage and robustness to PVT (power, voltage, temperature) are all important metrics for a high quality clock grid design. Tree-driven-grid clock network is a typical clock grid clock network. It includes a clock source, a buffered tree, leaf buffers, a mesh clock grid, local...
In this paper, we propose a technique for dynamically routing packets within a hierarchical network on chip (NoC). The concept of a local router range (analogous to other forms of locality awareness) determines on which hierarchy level a packet should be routed. In previous work, the degree of this locality awareness was static and uniform across the entire network. This paper shows that, using a...
3D integration is an emerging interconnect technology that can enable the continuation of performance scaling and the reduction of form factors. There are various approaches for 3D integration, including system-in-package (SiP), TSV-based 3D ICs, monolithic 3D ICs, and inductance/capacitance coupling 3D ICs, among which TSV-based 3D IC is the most promising one. This paper provides a summary of previous...
Delivering high quality power to the on-chip circuitry with minimum energy loss is an essential component of integrated circuits. The quality of the power supply can be efficiently addressed with multiple power supplies and decoupling capacitors integrated on-chip close to the points-of-load. Distributed power delivery requires the co-design of hundreds of power converters with thousands of decoupling...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.