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A quad-channel, 112–128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9–32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2Vpp-diff with 1.3 ps deterministic jitter (DJ). The DP-QPSK TX's precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing...
A 320×240 single photon avalanche diode (SPAD) based single photon counting image sensor is implemented in 0.13µm imaging CMOS with state of the art 8µm pixel pitch at 26.8% fill factor. The imager is demonstrated operating as a global shutter (GS) oversampled binary image sensor reading out at 5.14kFPS. Frames are accumulated in real time on FPGA to construct a 256 photon/8bit output image at 20FPS.
We present a 72×60, angle-sensitive single photon avalanche diode (A-SPAD) array, able to perform lens-less 3-D fluorescent lifetime imaging. A-SPAD pixels are comprised of (1) a SPAD to resolve precise timing information, reject high-powered UV stimulus, and map the lifetimes of different fluorescent sources and (2) integrated diffraction gratings over the SPAD to extract the incident angle of light,...
A data-driven machine learning processor (D2MLP) with MIMD architecture is designed for big data analysis. Adopting the configurable counting engine array with 3-layer dimension merging, the D2MLP processes maximal 1–128/1024 dimensional data with parallel 64/8 queries in learning stage. Implement in 90nm CMOS technology, the D2MLP achieves 219.9x and 8.2x faster processing time than CPU and GPGPU,...
A block downconversion receiver incorporates a digital image rejection technique to support multiple aggregated carriers by one receive path and one frequency synthesizer. A prototype consisting of a CMOS RF front end and an FPGA back end exhibits an image rejection ratio (IRR) of at least 70 dB across 2 GHz ± 25 MHz and reconstructs a −76-dBm 64-QAMsignal with an EVM of −30 dB in the presence of...
We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-µm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and Vt variability, thanks to delta-reset...
Application-aware solid-state drives (SSDs) with 2 adaptive coding schemes to improve reliability are presented. In NAND flash memory, a direct reliability trade-off exists between write/erase (W/E) cycle and data-retention (DR) time. Thus, SSDs can be used for applications that have long DR time and low W/E cycles, or short DR time with high W/E cycles. The n-out-of-8 level cell (nLC) scheme is proposed...
This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (IML-M), 2) reduce ML parasitic load (CML), 3) decouple NVM-stress from wordlength (WDL) and IML-MIS. RCSD reduces NVM-stress by 7+x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128×32b RCSD nvTCAM macro was fabricated using HfO...
On-chip jitter measurement is demonstrated in a 10Gb/s CDR by correlating the phase detector outputs of two adjacent CDR lanes. The RMS jitter of the received data and an estimate of the jitter's power spectral density are then extracted without using an external reference clock. Circuits implemented in 65nm CMOS measure random jitter ranging from 0.85ps to 1.89ps in PRBS31 data with no more than...
A 65-nm CMOS monolithic optical receiver IC with on-chip photodetector (PD) using the p-well/deep-n-well (PW/DNW) junction is presented for short-range optical communication using 850-nm wavelength. An adaptive continuous-time linear equalizer (CTLE) with 33-dB tunable gain is employed to compensate for the limited PD responsivity and bandwidth. For 850-nm optical PRBS-15 inputs, the receiver achieves...
A multi-modal spectroscopy IC combining the impedance spectroscopy (IMPS) and the multi-wavelength near-infrared spectroscopy (mNIRS) is proposed for high precision non-invasive glucose level estimation. A frequency sweep (10kHz – 76kHz) sinusoidal oscillator (FSSO) is proposed for high resolution (500 steps) for IMPS. The output voltage swing of the FSSO is stabilized by an adaptive gain control...
A time-based PID compensator that combines the advantages of both analog and digital controllers is used to implement a high frequency low quiescent current buck converter. Fabricated in 180nm CMOS process, the proposed buck converter operates over a wide range of switching frequencies (10–25MHz) and achieves better than 94% peak efficiency while consuming a quiescent current of only 2µA/MHz.
A series of high-sensitivity reactance sensors at 6.5/11/17.5/30-GHz is demonstrated for dielectric spectroscopy sensing on a single micron-size biological specimen. SNR is enhanced with the combination of interferometry and injection-locked oscillator sensors while the offset incurred by chopping-ripple is reduced through ping-pong nested chopping. The sensors achieve a sensitivity of less than 1...
An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The...
This paper presents a single inductor energy harvesting and power management (EHM) unit for ultra-low power (ULP) systems. The proposed circuit harvests energy from solar cells from 0.38V input voltage (Vin) and provides 4 output voltages - storage at 5V and VDDs at 3.3V, 1.5V and 1.2V. A peak inductor current control scheme enables high efficiency operation across wide input and output voltage range...
The Symposium on VLSI Circuits is sponsored by the IEEE Solid-State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers of Japan.
A 12-bit Hybrid DAC architecture with split Nyquist (1GS/s) and delta-sigma modulator path (8GS/s) has been proposed and implemented in 65nm CMOS. Based on the hybrid architecture, the delta-sigma assisted pre-distortion scheme compensates for the current steering cell mismatch that further reduces the analog circuit complexity and area. The proposed 8X unrolled pipeline delta-sigma modulator allows...
A 9-bit 11GS/s current-steering (CS) digital-to-analog converter (DAC) is designed in 28nm FDSOI. The DAC uses two-times interleaving to suppress the effects of the main error mechanisms of CS DACs while its clock timing can be tuned by the back gates bias voltage of the multiplexer transistors. The DAC achieves higher than 50dB SFDR and less than −50dBc IM3 over Nyquist at a sampling rate of 11GS/s,...
In the years between now and 2020, we should expect continued exponential data growth [15][16]. A number of ongoing advances in storage: the transition to solid-state drives (SSDs), the scaling of NAND flash capacity, and advanced silicon packaging techniques will dramatically increase the capacity of storage subsystems over the same timeframe. This will significantly reduce the ratio of storage bandwidth...
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