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Electron spin attracts much attention as an alternative degree of freedom for low-power reprogrammable logic and non-volatile memory applications. Silicon appears to be the perfect material for spin-driven applications. Recent progress and challenges in simulating spin-based devices are briefly reviewed. Strain-induced enhancement of the electron spin lifetime in silicon thin films is predicted and...
In order to enable the simulation of statistical variability simulation in non-ideal device structures which arise from complex patterning steps, the GSS atomistic simulator, GARAND, has been enhanced for handling arbitrary 3D device geometries, and a structure translation tool MONOLITH has been developed to transfer the information about the device geometry, material composition and doping distribution...
Recently, we proposed an alternative nonvolatile magnetic flip flop which allows high integration density. This work extends the up to now gained results to the devices' functionality under statistically distributed magnetization variations of its free layer. Assuming position uncorrelated random fluctuations in the free layer, that the variations are fixed with respect to time, and that small deviations...
Complementary MOSFET and Tunnel-FET inverters based on tri-gated strained Si nanowire arrays are demonstrated. The voltage transfer characteristics as well as the inverter supply currents of both inverter types are analyzed and compared. A degradation of the inverter output voltage is observed due to the ambipolar TFET characteristics. Emulated TFET inverters based on the measured transfer characteristics...
We report for the first time a quantum mechanical simulation study of gate capacitance components in aggressively scaled InAs Tunnel Field-Effect Transistor (TFET) nanowires. It will be shown that the gate-drain capacitance follows the same trend as the total gate capacitance (but with smaller values) over the whole Vgs range, hence confirming the capacitance estimation provided by semiclassical TCAD...
We investigate the effect of interface states at the channel/insulator interface of III-V MOSFETs by means of accurate Schro¨dinger-Poisson and Multi-subband Monte Carlo simulations. Traps in the conduction band are found to be the main responsible of the Fermi level pinning observed in the experiments. These traps impact the mobility measurements as well as the current drive of short channel devices.
A simple analytic model based on the Kane-Sze formula is proposed to describe the current-voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model has fairly general validity and is not specific to a particular...
We report on a wafer scale fabrication of graphene based field effect transistors (GFETs) for use in future radio frequency (RF) and sensor applications. The process is also almost entirely CMOS compatible and uses a scalable graphene transfer method that can be incorporated in standard CMOS back end of the line (BEOL) process flows. Such a process can be used to integrate high speed GFET devices...
It is known that the fabrication of graphene NEMS raises several technological issues. Beyond capillarity effects, the quality of the interface between graphene and resist is the most critical challenge. In this paper we propose a high yield route for the fabrication of suspended graphene structures, using technological steps compatible with large-scale fabrication. AFM and Raman characterization...
We report the results of a multi-scale transport modeling of ultra-narrow GNRs. Atomistic NEGF approach is combined with semiclassical mobility modeling in order to quantify the sensitivity of mobility to edge defects. We find that the mobility in defected GNRs deteriorates more strongly as GNR width is scaled down compared to ideal devices, and that even the minimum mobility variation spans almost...
A compact and low cost hybrid system enabling AC real-time measurements, as well as impedance characterization of bio-nanosensors is presented. The instrument has been tailored for nanowire-based sensors and sensing is measured with performing amperometric techniques with lock-in to measure the complex impedance detection. In addition to the magnitude of the impedance, the system also measures the...
A novel device technology for photonics integrated circuits (PICs) is presented. In this work germanium PIN photodetectors are embedded in back-end deposited high-k slot waveguides. The waveguides are fabricated using chemical vapor deposited amorphous silicon and atomic layer deposition of Al2O3 thin films. The germanium PIN stack is selectively grown on a bulk silicon substrate. The detectors are...
This paper presents an experimental study of the piezoresistive (PR) coefficients in silicon nanowire (NW) transistors as a function of NW width down to 10nm. We have evidenced the variation of these coefficients as the width shrinks from wide SOI down to nanowire transistors, for both NMOS and PMOS. Below a critical width Wcrit ≈ 100nm, the longitudinal PR coefficient is improved for electrons, whereas...
This work presents an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance gm, the output conductance gd, the intrinsic gain Av and the cut-off frequencies ft and fmax. Firstly, 28 nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly,...
We report an experimental investigation of oxide/channel interface quality in SOI omega-gate nanowire NMOS FETs with cross-section as small as 10nm×10nm by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, H2 anneal, or channel orientation. A method for rigorous contribution assessment...
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