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3D integration using through-silicon vias offers many benefits, such as high bandwidth, low power, and small footprint. However, test complexity and test cost are major concerns for 3D-SICs. Recent work on the optimization of 3D test architectures to reduce test cost suffer from the drawback that they ignore potential uncertainties in input parameters; they consider only a single point in the input-parameter...
A method of testing for parametric faults in analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the root mean square (RMS) magnitude of the applied input voltage at a relevant frequency or DC. The test then classifies the CUT as fault-free or faulty based upon a comparison...
Due to the current hardware and testing environment limitations, sometimes a perfect coherent condition cannot be satisfied regarding Digital-to-Analog Converter testing. In this paper, the existing algorithms for non-coherent sampling are reviewed and the limitations of each algorithm are analyzed. Then an enhanced procedure is proposed with detail explanation. The experimental results show the new...
One of the primary goals of ITC is to serve the professional and academic communities by presenting the highest quality technical program to its attendees. A key element in achieving this goal is the evaluation and selection process developed by the ITC Program Committee. In this process, the committee must meet two requirements: evaluate paper submissions on merit as determined by thorough, fair...
The requirements for the recent mobile devices are significantly different from those for the conventional PC-oriented devices in many aspects: power consumption, performance and production ramp-up speed. These unique requirements have created many challenges in process technology, design, and manufacturing. Mobile devices are battery-sensitive, but still need the horsepower to run performance-hungry...
Intel architecture scales from Exa-scale computing to hand-held and deeply embedded devices. A consistent architecture spanning many product domains brings benefits to silicon and product developers. But it also creates a validation challenge that is nonlinear in nature due to the differences in product complexity, use cases, and user expectations. In this talk, John will address how Intel views the...
The cost of maintaining current levels of hardware reliability appears to be unaffordable in the post-22 nm late CMOS design era. In the first part of this talk, we will examine the reasons behind such a projection, based on the modeled trends in technology, circuits and microarchitecture. Then, in the second part, we will present a vision of cross-layer resilience optimization, which forms the basis...
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