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A 900-MHz system is designed to harvest ambient RF energy and generate 2-V output voltage. An efficient power path structure with adaptive control is proposed to maintain close-to-optimal power conversion efficiency. The control circuit consumes low power by adopting a novel open-loop asynchronous control scheme and duty-cycled operation. A startup circuit is also presented. Measurement results show...
This paper presents a self-calibrating RF energy harvester capable of harvesting at lower input power levels than current state-of-the-art RF harvesters. A 5 stage cross-connected bridge rectifier is brought at resonance with a high-Q loop antenna by means of a 7-bit binary weighted capacitor bank. A control loop compensates any variation in the antenna-rectifier interface and passively boosts the...
We propose a maximum power point tracking (MPPT) circuit for micro-scale sensor systems that measures ripple voltages in a switched capacitor energy harvester. Compared to conventional current mirror type MPPT circuits, this design incurs no voltage drop and does not require high bandwidth amplifiers. Using correlated double sampling, high accuracy is achieved with a power overhead of 5%, even at...
A 6.0-W bi-directional DC-DC converter has been developed for a wireless power transceiver which enables a mobile device to receive and transmit power wirelessly. When transmitting power, a mobile device can function as a wireless power station for another mobile device. Implemented in a 0.35-µm BCDMOS process, the DC-DC converter shows 91-% peak efficiency and the wireless power transceiver employing...
Battery monitoring systems are a critical aspect of electric vehicles. To interface with the high voltages in these systems a stacked IC approach is used. In this work we present an IC suitable for monitoring 6 cells which can be stacked to monitor a total of 192 cells. The IC has 13 parallel ΣΔ ADCs (12 bit, 5mV accuracy, better than 1.5mV matching) to measure individual cell voltages, cell temperature...
This paper presents a quarter-rate forwarded clock (FC) receiver based on an injection-locked oscillator (ILO) which exploits a phenomenon that phases of the output clock are shifted by the duty cycle of an injection clock. To utilize this phase shifting phenomenon, a simple duty cycle adjuster (DCA) is proposed. By using the DCA, the proposed FC receiver achieves 760MHz of wide jitter tracking bandwidth...
We propose and demonstrate an 8 to 16GHz clock distribution circuit using mutual-injection-locked ring oscillators. It distributes synchronous clock signals by mutually coupling the neighboring ring oscillators through the transconductors. It enables low swing clock distribution with minimal load capacitance, resulting in the fastest among the injection-locked ring-oscillator-based clock distribution...
A 5Gbp/s mobile memory I/O interface at sub-1.0V supply voltage with Low Voltage-Swing Terminated Logic (LVSTL) using a VSSQ (Ground) termination and an adaptive reference voltage calibration scheme is presented. Power efficiency is 2.4mW/Gbps/pin in 20nm mobile DRAM process, which is 44% lower value than that of LPDDR3.
This paper describes DLL architecture and ZQ calibration method for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM. Proposed DLL consists of one DLL with CML DCDL and another DLL with CMOS DCDL which tracks first one for low jitter and low power characteristics. Quantization error minimized (QEM) ZQ calibration is proposed for better signal integrity and yield improvement. The implemented DLL dissipates 6.5mW...
A fast lock DLL based 800Mb/s to 3.2 Gb/s burst mode memory interface is implemented. The DLL employs a two-step TDC during power up from 0mW to lock within 3 cycles with residual error < 33 mUI. Following initial lock, the DLL operates closed-loop to compensate for V,T drift consuming 6mW @ 1.6GHz. In addition the DLL filters high frequency input jitter and corrects 20% DCD without additional...
A highly adaptive multi-sensor SoC comprising four on-chip sensors and a smart wireless acquisition system is first realized in standard CMOS process. To intelligently process different types (C/R/I/V) of sensor signals, a linear (R2 = 0.999) and reconfigurable sensor readout is proposed. A two-input energy harvesting interface with conversion efficiency of 73 % is also integrated for long-term use...
Data-driven methods based on machine learning enable powerful frameworks for analyzing complex physiological signals in medical-sensor applications; however, these methods are not well supported by traditional DSPs. A general-purpose microprocessor is presented in 130nm CMOS that integrates configurable accelerators, enabling low-energy hardware to support the broadest range of machine-learning frameworks...
A machine-learning (ML) assisted cardiac sensor SoC (CS-SoC) is designed for healthcare monitoring with mobile devices. The architecture realizes the cardiac signal acquisition with versatile feature extractions and classifications, enabling higher order analysis over traditional DSPs. Besides, the dynamic standby controller further suppresses the leakage power dissipation. Implemented in 90nm CMOS,...
This paper presents an ultra-low-power filter bank design for digital hearing aids. A novel time borrow & local boost (TBLB) scheme for aggressive voltage over-scaling is proposed, which does not incur cycle penalty on the rescue of timing violations, and is thus suitable for hardwired ASIC. The measured power of the test chips with the straightforward filter implementation can outperform those...
A versatile signal reconstruction platform designed in a 40nm CMOS process is presented. The chip supports high-dimensional sparse signal reconstruction for compressed sensing and sparse representation. A 4G entries/s (8Gbps) high-throughput sensing matrix generation engine is proposed. It r educes o ver 7 5% external bandwidth and 77% processing cycles. The chip achieves 401GFlops/W power efficiency...
An asynchronous 8× interleaved redundant SAR ADC achieving 8.8GS/s at 35mWand 1V supply is presented. The ADC features pass-gate selection clocking scheme for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC stacks the capacitive SAR DAC (CDAC) with the reference capacitor to reduce the area and enhance the settling speed. It achieves 38...
A 13-bit current-steering DAC-based transmitter prototype is integrated into a 28nm CMOS SoC for broadband communication systems. The DAC uses a segmented structure with a focus on high speed, low noise, and low distortion. A novel LDO is also proposed for better spur tolerance in hostile SoC environments. The transmitter achieves > 70dBc SNDR within the 50–1000MHz cable band for single QAM channel...
This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes...
An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in...
A 410 MS/s 2x interleaved 11bit pipelined SAR ADC in 28nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR and includes an on-chip calibration engine that detects and corrects comparator offsets and amplifier gain errors in the background. The ADC achieves a peak SNDR of 59.8 dB at 410 MS/s for an energy per conversion step of 6...
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