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Negative Bias Temperature Instability (NBTI) is a major reliability issue in nanoscale VLSI systems. Previous work has shown how the exploitation of conventional optimization techniques can reduce the NBTI-induced aging in cache memories. Other works have proposed approaches that incorporate software directed data allocation strategies to partially recover from NBTI-induced aging in Scratchpad Memories...
Three-dimensional (3-D) memory stacking is one of the most promising solutions to tackle memory bandwidth problems in chip multiprocessors. In this work, we propose an efficient runtime 3-D cache management technique which not only takes advantage of the low memory access latency through vertical interconnections, but also exploits runtime memory access demand of applications which varies dynamically...
A stable voltage supply is critical for multiprocessor system-on-chips (MPSoCs) to operate at near-optimal performance levels. The problem of IR drops in a Power Delivery Network (PDN) is very severe in 3D MPSoCs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally with the number of device layers. At the same time, with the increasing core counts in today's power-hungry...
A 3D architecture with DRAM memory stacked on a multi-core processor has many benefits for the embedded system. Compared with a conventional 2D design, it reduces memory access latency, increases memory bandwidth and reduces energy consumption. However it poses a thermal challenge as the heat generated by the processor cannot dissipate efficiently through the DRAM memory layer. Due to the fact that...
As conventional CMOS technology is approaching scaling limits, the shift in trend towards stacked 3D Integrated Circuits (3D IC) is gaining more importance. 3D ICs offer reduced power dissipation, higher integration density, heterogeneous stacking and reduced interconnect delays. In a 3D IC stack, all but the bottom tier are thinned down to enable through-silicon vias (TSV). However, the thinning...
We propose a new test array architecture—vertically-addressed test structures (VATS)—to experimentally characterize the within-tier and tier-to-tier process variations and through-silicon via (TSV) induced stress in 3D integrated circuits (ICs). The proposed VATS architecture utilizes the benefits of 3D integration to simultaneously provide high density, low I/O pin utilization, and high fidelity...
This paper presents a self adaptive architecture to enhance the energy efficiency of coarse-grained reconfigurable architectures (CGRAs). Today, platforms host multiple applications, with arbitrary inter-application communication and concurrency patterns. Each application itself can have multiple versions (implementations with different degree of parallelism) and the optimal version can only be determined...
State-of-the-art General-Purpose computing on Graphics Processing Unit (GPGPU) is facing severe power challenge due to the increasing number of cores placed on a chip with decreasing feature size. In order to hide the long latency operations, GPGPU employs the fine-grained multi-threading among numerous active threads, leading to the sizeable register files with massive power consumption. Exploring...
Stream architecture is emerging as an important architecture for performance improvement of media applications. With technology scaled to nanometer-scale, leakage energy consumption is accounting for a greater proportion of the total energy consumption than ever, especially for stream architectures with a large number of functional units. In this paper, a compiler-assisted instruction-level scheduling...
We present a novel and highly automated technique for dynamic system level power management of System-on-a-Chip (SoC) designs. We present a formal system to represent power constraints and power intent as rules. We also present a Term Rewriting Systems based rule rewriting engine as our dynamic power manager. We provide a notion of formal correctness of our rule engine execution and provide a robust...
Wireless Network-on-Chip (WiNoC) has emerged as an enabling technology to design low power and high bandwidth massive multi-core chips. The performance advantages mainly stem from using the wireless links as long-range shortcuts between far apart cores. This performance gain can be enhanced further if the characteristics of the wireline links and the processing cores of the WiNoC are optimized according...
Vector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting data-level parallelism. Previous research on vector architectures predominantly focused on performance, so vector processors require a new design space exploration to achieve low power. In this paper, we present a design space exploration of adder unit for vector...
In signal processing applications, large energy gains can be obtained by accepting some degradation in the output signal quality. Filters are at the core of many such systems. In this paper, we demonstrate the potential of a new paradigm for achieving favorable quality-energy trade-offs in digital filter design that is based on directly accepting timing errors in the datapath under aggressively scaled...
In this paper, we propose a novel and efficient iterative method for pad placement optimization of power grid with flip chip technology. Power grid with optimized pad placement has less IR-drop values. We develop a new method to calculate new locations of all pads. Placing pads at the new locations reduces local IR-drop values. In order to reduce global IR-drop values, we develop a graph-based strategy...
In this paper, we address the problem of scheduling operations into control steps with dual threshold voltage (dual-Vth) technique under timing and resource constraints. We present a min-cut based algorithm for leakage power optimization. The proposed algorithm first initializes all the operations to high-Vth, then iteratively shorten the critical path delay by reassigning the set of operations covering...
Model-free reinforcement learning (RL) has become a promising technique for designing a robust dynamic power management (DPM) framework that can cope with variations and uncertainties that emanate from hardware and application characteristics. Moreover, the potentially significant benefit of performing application-level scheduling as part of the system-level power management should be harnessed. This...
Efficient thermal analysis plays a key role in the temperature-aware floorplan design for MultiProcessor System-on-Chip (MPSoC) and Dynamic Power& Temperature Management (DPTM). This work adopts the bottom-up modeling method to study architecture-level MPSoC thermal analysis. First, it extracts relative thermal resistance between functional modules with HotSpot software. Then, based on these parameters,...
In this paper, we propose an application-driven ALU design methodology to achieve high level of power efficiency for modern microprocessors. We introduce a PN selection algorithm (PNSA) which enables designers to select power efficient dynamic modules for different applications, based on the detailed analysis of dynamic circuits. Experimental results on ISCAS85 and 74X-Series benchmark circuits show...
CMOS Digital signal processing hardware are power efficient but consume large area, whereas, analog processing units, based on CMOS technology are compact, but power hungry. Emerging magneto-metallic spin-torque devices like domain wall magnets can however perform analog-mode computation like summation and thresholding at ultra low voltage. Such devices can be exploited in designing spin-CMOS hybrid...
The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of...
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