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In signal processing applications, large energy gains can be obtained by accepting some degradation in the output signal quality. Filters are at the core of many such systems. In this paper, we demonstrate the potential of a new paradigm for achieving favorable quality-energy trade-offs in digital filter design that is based on directly accepting timing errors in the datapath under aggressively scaled...
Network-on-Chip has been proposed for high performance on-chip communication. The major component of a Network-on-Chip architecture is the router, which affects the data transmission latency, chip area and power consumption. Inside the router, buffers occupy a significant a mount of power and a large partition of chip area. Therefore bufferless NoC, which discards the buffers in the routers, has been...
As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. We address this by evaluating Tunnel FETs (TFETs) for use in low-power, high-performance flip-flop designs...
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