The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The effect of the film thickness of the ferroelectric barium strontium titanate thin films at the memory behavior of ferroelectric-gate field effect transistor (FeFET) has been studied. The films have been fabricated as metal-ferroelectric-insulator-semiconductor (MFIS) configuration using sol-gel technique. In order to investigate the memory window behavior, the C-V measurements have been carried...
Effects of post-deposition annealing was performed at different annealing temperatures (600, 800, and 1000°C) onto metal-organic decomposed lanthanum cerium oxide film spin-coated on Si substrate. X-ray diffraction analysis had detected four diffraction peaks of lanthanum cerium oxide in all of the investigated samples. Additional peak associated to lanthanum silicate (La2Si2O7) was detected in sample...
The Semiconductor Industry Association (SIA) expectations are to achieve the 22nm technology at the end of 2018. So aggressively continuation in physical size scaling of Complementary Metal Oxide Semiconductor Transistor (MOSFET) experiences difficulties due to various factors. The conventional oxide can be scaled down to two atomic layers of about 7 A because of limitations of leakage current, interface...
The Semiconductor Industry Association (SIA) expectations are to achieve the 22nm technology at the end of 2018. So aggressively continuation in physical size scaling of Complementary Metal Oxide Semiconductor Transistor (MOSFET) experiences difficulties due to various factors. The conventional oxide can be scaled down to two atomic layers of about 7 A˚ because of limitations of leakage current, interface...
CMOS transistor reaches physical and electrical limitations technology passes through the critical 90 nm gate size. Scaling down linearly to 35nm, the transistor electrical characteristics behave even more unpredictable. This can be seen with leakage current increasing exponentially as the physical size reduced linearly, mainly caused by the short channel effect. As a result, the threshold voltage...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.