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Recently, CMOS downsizing has been accelerated very aggressively in both production and research levels, and even beautiful transistor operation of several nm gate length CMOS devices were reported in conferences. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits. It is still questionable if we can successfully introduce deep sub-10...
This paper is to study the characteristics of nanowire-CMOS and effect of increasing of numbers of nanowires in transistors on the nanowire-CMOS characteristics. This study used MuGFET simulation tool to produce the characteristics of nanowire transistors and used as input to MATLAB software to produce the characteristics of nanowire-CMOS. Increasing channel nanowires in P-channel transistor tends...
This paper presents a fully integrated CMOS up-conversion mixer with input active balun at 5.2 GHz for wireless applications. The design based on Gilbert-cell active double-balanced mixer with integrated on-chip input active balun is proposed by using TSMC 0.18 μm technology. Core mixer employs derivative superposition method to obtain high linearity. A designed active balun which converts single-ended...
This paper introduces a complete methodology for analogue layout design using a concept of cells and arrays for analog layout generation, migration and reuse. With careful integration of the device sizes and layout generation tasks, a fully functional layout designs are able to be generated in a few steps and fraction of time. This paper describes such a system and shows its importance in obtaining...
This paper presents the feasibility challenges of designing dc-dc buck and boost converter in nano-scale. With the gradual development of VLSI design platforms, new issues have been introduced and presented to the power electronics circuit experts and VLSI engineers. Today's VLSI industry has reached the technology well within the nano-meter range. The consequence of implementing the basic power electronics...
The aim of this paper is design of interface circuit while it is applied in capacitive sensor applications. In this paper, the circuits were designed in 0.18-μm Silterra CMOS technology and simulated in Mentor Graphic DA-IC. The proposed capacitive sensor includes two major building blocks: a wide-swing current mirror with enhanced output impedance which is usually used in wide-signal-swing op-amps,...
This paper discusses the design and analysis of a latching comparator using charge sharing circuit topology for low power and high speed. This topology combines the good features of the resistive dividing comparator and the differential current sensing comparator. This design will be focusing on the minimization of propagation delay and the power dissipation of the comparator, which will improves...
This paper proposed the design of a switchable dual-band low-noise amplifier (LNA) using Silterra 0.18-μm CMOS technology fabrication process. The LNA utilized the single-ended type with cascode inductively source degeneration topology. This topology is best for simultaneous noise and input matching besides capable of reducing the Miller effect as well as improving on the reverse isolation performance...
Operational amplifier (Op amp) is the most integral part of an embedded circuit building block. In this paper, the testing of an integrated Op amp suitable use for capacitance and high speed measuring system has been made. The Op amp testing (such as large signal differential transfer characteristic, frequency respond analysis, input common mode analysis, slew rate analysis) has been done using the...
The evolution of portable telecommunication devices are accredited to semiconductor down-scaling and high-integration of IC circuits and have enhanced user experience. However there is still some inefficiency faced by the Public Safety sector utilising portable communication due to lack of interoperability between different agencies. This paper simulates and compares the frequency response of active...
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