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High performance implementation of 2D digital filters are highly desired in many applications for real-time processing. In this paper, a multiprocessor realization of a 2D denominator separable digital filter is implemented in Altera Stratix III FPGA. The implementation achieves a data throughput equivalent to one multiplication and two additions, plus one clock cycle. It has been found that the maximum...
This paper presents a performance-optimized version of the flexible triangle (FTS) block-matching search algorithm. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work that, given a block of pixels, is used to search for the best-matching block in a given search area using only a selected subset of available positions rather than searching all available positions...
One of the issues of power amplifier used in satellite communications is its nonlinearity. Digital predistortion is used in a linearizer to inverse this undesired effect to achieve higher efficiency to the amplifier. Xilinx provides a predistortion core to be implemented in FPGA devices. The core is used in a linearizer to test its functionality and performance. Simulation results indicate a gain...
Catastrophe events can happen when a computer or a computer network is exposed to the Internet without any security protection. The security issues can be mitigated by setting up a firewall between the inside network and the outside world. This paper describes a design of a highly customizable hardware packet filtering firewall to be embedded on a network gateway. A packet filtering firewall controls...
Dense stereo disparity map provides a robust method on distance measurements in a 3D scene. Due to its computational complexity in nature, it has been a challenge to achieve real-time processing. In the past years, various algorithms have been studied in order to reach the goal of real-time processing. In this paper, a Dynamic Time Warp (DTW) algorithm is proposed. The DTW algorithm provides excellent...
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