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For SoCs (Sea of Cores!) which contains a large amount of IP cores with pre computed test data, the code based test data compression scheme is more suitable as it does not require any knowledge of internal nodes of IP. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In this paper, the five different approaches for don't care...
This paper describes an algorithm for generating test signals to efficiently test the linearity of ADCs. Linearity is an important testing item for ADCs, and it takes a long time (hence is costly) to test low-sampling-rate, high-resolution ADCs. We here propose to generate a test signal consisting of multiple sine waves, to precisely test the linearity for specific important codes (such as around...
This paper investigates the challenges of a 3D-stacked system-on-chip testing, especially in terms of thermal problem. It is known that test power can be more than twice the intended power dissipation of the chip in the functional mode, for a single die. This problem is exacerbated when more than one dies are stacked on top of each other in a single package. Without proper test strategies, the thermal...
Network-on-Chip (NoC) is becoming a promising communication architecture for the next generation embedded cores based system chips. The reuse of NoC as test access mechanism (TAM) for the embedded cores reduces the test time of the system. However, NoC reuse is limited by the on-chip routing resources and some other constraints. Therefore, efficient test scheduling methods are required to provide...
This paper describes a vision-based lane detection system with the optimized Hough Transform circuit. The Hough Transform is a popular method to find the line features in an image. This is very robust to noises and changes in the illumination level, but it requires long computation time and large data storage for calculation. It needs large logic gates for implementation. It is difficult to apply...
This paper presents the design of an output-capacitor-free cascode low-dropout regulator (LDR) with low quiescent current and high power supply rejection (PSR) over a wide range of frequency. In the proposed LDR topology, power NMOS transistors are cascoded to isolate the core regulator from power supply ripples, thus providing high PSR even without any external filtering capacitors. By biasing the...
System-on-chip technology requires smooth interfacing between its various peripherals and processors. Multi-channel Analog-to-Digital Converter with high speed and serial interface even raises more challenges to the designer in order to interface the ADC with processor. In this paper, we present the interface design between a multi-channel ADC and high speed DSP processor for system-on-chip design...
We present a concise, fast, accurate, efficient mixed-level full-system based realistic application-oriented simulation platform in this paper which aims to evaluate the cycle-accurate behavior of interconnection component thus help developers to explore more optimized NoC architecture. A trace-driven transaction-level simulation environment is built to get realistic traffic patterns for interconnection...
This paper describes a circuit design methodology to optimize both power and jitter performances of the inductorless voltage-controlled oscillators (VCOs) by utilizing an on-chip supply noise monitoring circuit. As the phase-locked loop (PLL) has a sensitive response to the noise frequency near the loop bandwidth, detecting low frequency tones up to the PLL bandwidth is considered for a supply noise...
This paper describes a set of state-of-the-art race logic synthesis technologies for multithreaded/multi-core HDL (hardware description language) and ESL (electronic system level) simulators, such as V2Sim™ [1]. The new technologies aid V2Sim™ to automatically eliminate race logic in large-scale System-on-Chip (SoC) circuits [2.3], so that V2Sim™ multithreaded simulation results will be the same as...
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