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This paper describes a design strategy that makes viable hardware implementations of Information-Set (IS)-based decoders with near-MLD performance. This is achieved through three main developments: i) a criterion that reduces the number of candidate codewords, without significant performance loss; ii) a modified, hardware-friendlier version of the Dorsch algorithm; and iii) detailed circuit analysis...
This paper presents a novel architecture for the FPGA-based implementation of multilayer neural network (NN), which integrates the layer-multiplexing and pipeline architecture together. The proposed method is aimed at enhancing the efficiency of resource usage and improving the forward speed at the module level, so that a larger NN can be implemented on commercial FPGAs. We developed a mapping method...
This paper presents the design and FPGA implementation of a 24-bit audio DAC incorporating a set of multiplier-free interpolation filters and a 4th-order 1-bit sigma-delta modulator (SDM). The whole system achieves a signal to noise ratio (SNR) as high as 139dB with idle tones and noise modulation virtually eliminated. For the fixed point interpolation filters, multiplier-free canonical signed digits...
Image pulse sensors provide pixels information with a series of pulse train considering Pulse Frequency Modulation (PFM). PFM sensors are often used in vision chips considering related advantages. In this paper, edge detection and contrast enhancement algorithms are analyzed and simulated using pulse domain techniques of suppression and promotion. Comparing with classical methods, pulse-domain-based...
An extended version of low-complexity IP Core for image/video transformations based on the CORDIC architecture is presented. This IP core is able to perform quantized 8×8 IDCT and quantized 8×8/4×4 H.264-inverse integer transforms on a configurable architecture by using only shift and add operations. Furthermore, the number for CORDIC iterations and compensation steps can be adjusted, which enables...
This paper describes the Panning Sorter (PanS), a new architecture for hardware implementation of compact, fast, low power data sorters operating with parallel inputs. The proposed approach is compared against several other contemporary implementations (Systolic, Bitonic, Weave, and Insertion sorters) in order to demonstrate its features. The PanS architecture is then extended to the implementation...
The design, simulation, fabrication, and characterisation of a silicon single photon avalanche diode (SPAD) array with integral quenching and discriminator circuits is presented. The array is a 16×1 parallel output SPAD array which comprised active quenched SPAD circuit in each pixel, and was fabricated in a UMC 0.18μm CMOS process. The SPADs were operated in the Geiger mode where the applied reverse...
This paper proposes a scheme that can detect SEU errors occurring in an FPGA configuration SRAM cell (CRAM) in a time-efficient manner (>;40X faster or<;2 ms). The concept and design implementation of the proposed scheme is described in detail. This is a low-cost solution as most of the implementation reuses existing circuits. In addition, the benefits of the proposed schemes are discussed.
3D IIR beam/cone filter-banks are derived from beam transfer functions of 2D/3D LC-ladder low-pass networks. Such filters are obtained using 3D frequency-planar filters as building blocks, and lead to highly-selective RF beamforming capabilities over wide bandwidths. High computational complexity necessitates high-performance computational hardware for useful throughput. A massively-parallel systolic-array...
Space Vector PWM (SVPWM) model is often built based on high-level functions and verified based on the output of the inverter or the model of the electrical motor with best possible accuracy. However, SVPWM implementation on digital hardware such as Field Programmable Gate Array (FPGA) and Application-specific Integrated Circuit (ASIC) is constrained by the limited resources and computation accuracy...
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