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This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed...
A multiloop method is presented for highly nonlinear ring oscillators in this paper. This circuit permits lower tuning gain through the use of coarse/fine frequency control, which also translates into a lower sensitivity to the voltage at the control lines. A 8-GHz VCO in SMIC 0.18μm 1P6M CMOS technology is designed. The linear tuning range of VCO is from 7.95 to 8.45GHz with the tuning voltage vary...
This paper presents a low-offset, low-power, high-speed comparator using bulk biasing calibration technique. The adjustment of bulk voltage is realized by analog integration in a feedback loop. The technique can calibrate the offset voltage to small value without reducing speed. The comparator is designed in a standard digital 65nm CMOS technology with 1V supply voltage. The comparator works at 1GHz...
SRAM sense amplifier plays a key role in memory design. With technology scaling to the nanometer, the device mismatch increases and the distribution effect induces unstable signal injection, thus affecting the reliability of memory system. This paper presents a new method for SRAM sense amplifier design. It incorporates reasonable delay between the passgate and enable signals to effectively mitigates...
The open-loop de-skewing circuits are traditionally used for fast clock synchronization, but they are unable to deal with the problems induced by run-time variations. This paper presents the design of a skew compensation circuit that can achieve fast lock-in and also perform maintenance operation after lock-in. This circuit is designed on top of the open-loop half-delay-line skew compensation circuit...
This paper presents the design of a low-power multi-channel time-based analog-to-digital converter (ADC) for the instruments dedicated to high-energy physic experiments and biomedical imaging applications. The proposed ADC is realized by using two-step conversion scheme: the voltage-to-time conversion (VTC) and the digital-to-time conversion (TDC). In VTC, the classic Wilkinson-type architecture are...
With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address...
A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional...
As an important implementation of Cryptographic algorithm, processor should be thought about the ability of resistant power attack. In this paper we show a processor architecture, which automatically detects the execution of the encryption algorithms, and interleaves the execution of cryptographic algorithm code with that of dummy instructions to reduce the correlations between the leakage and the...
An improved negative level shifter with high speed and low power consumption is presented. To reduce the switching delay and power consumption, a boost circuit is designed and additional charging current paths are introduced in the improved level shifter. The circuit has been designed in 130nm triple-well standard CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of -4...
This paper presents an optimized architecture of shared memory controller in packet processing multi-processor system on chip (MPSoC). The rotation priority algorithm in arbitration mechanism is ameliorated so that fairness of the memory access response and continuity of read/write commands are guaranteed. A `ping-pong' structure is adopted in SRAM interface logic which optimizes the memory data throughput...
With the amount of calculation for wireless and multi-media applications increasing, the Multi-Processor System-on-a-Chip (MPSoC) based on Network-on-Chip (NoC) is used to process massive data in a distributed fashion. Compared with heterogeneous architecture for general embedded low power DSP, homogeneous NoC architecture is much more flexible for dynamical task assignment. In this paper, a new NoC...
Our research project is to design a readout IC for an ultrasonic transducer consisting of a matrix of more than 2000 elements. The IC and the matrix transducer will be put into the tip of a transesophageal probe for 3D echocardiography. A key building block of the readout IC, a programmable analog delay line, is presented in this paper. It is based on the time-interleaved sample-and-hold (S/H) principle...
This paper described a digitally controlled Buck converter. In this converter, the compensator implements the classic linear PID control law by the fixed-point algorithm. A proposed verification method is performed in Simulink environment. The structure of low area and power cost Ring ADC and high resolution DPWM is also introduced, respectively. The consistent mathematic and Spice simulation result...
Based on the application of high-speed, high-resolution A/D converter, this paper describes the design and implementation of a novel high-speed comparator. The comparator uses the high-speed, transmission delay stability technology, the auto-zero technology, and the cascade technology in order for the comparator to have the high-speed, high-resolution, transmission delay stability features. Its performances...
In this paper, a low-cost VLSI implementation of a pipeline fast Fourier transform (FFT) processor capable of supporting from 1k to 32k FFT sizes is presented. The radix-22/23 based pipeline structure reduces the steps of normal complex multiplications, and the single-path delay feedback (SDF) memory access method ensures a minimum (N-1) memory words to get the FFT results. As for the data-path in...
In this paper a low swing driver-receiver pair (lhos-lp) for driving signals is proposed to optimize the energy dissipation and delay of global interconnect lines. The simulation, performed based on 1V 0.13μm CMOS technology with HSPICE, for signal transmission along a wire- length of 10 mm. The simulation results show lhos-lp is 18% and 14% better than other similar signaling schemes (lhos-db and...
In this paper, two novel structures at 200mV 0.18um sub-threshold full adders are proposed for wireless sensor network nodes or medical electronics. They use three state gate to enhance the transition time and drivability of carry out signal. Simulation results show that the transition time of the proposed structure using three state gate is 60% of that of old structure using transmission gate. The...
Scaling frequency and voltage in a coordinated manner is a promising way to reduce energy and power. we explore the use of dynamic frequency clocking within the datapath and datapath scheduling algorithms that can be incorporated into a datapath synthesis tool. Given a schedule, we propose a practical optimal frequency assignment algorithm based on dynamic programming. The algorithm run very fast...
Power Gating(PG) is very effective to reduce the leakage power. Recently proposed Zigzag power gating(ZPG) technique has the visible advantage on short wake-up time. However, additional PG transistors consume intolerable area overhead. Basing on the BPTM-65nm model, we propose a new optimization methodology of the selective ZPG technique for the wide-used dual-threshold voltage CMOS circuit design...
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