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A UWB receiver with carrier that has 400 MHz cut-off frequency, 73 dB dynamic range and -70 dBm input sensitivity was generated in 0.13 um CMOS technology for applying to the both IR and MB-OFDM UWB transceiver. LNA and VGA have the broad gain variation (27 dB and 51 dB respectively) using 2 bit and 6 bit switch control. The 7th order gm-C Chebyshev LPF utilizes the modified Nauta OTA and gyrator...
This paper describes the system architecture and design procedure for an integrated 60-GHz direct-conversion transceiver with integrated digital control interface on a 130-nm CMOS process. This transceiver incorporates both a transmitter and receiver. The transmitter achieves a Psat of 6.5 dBm, an OPldB of 1.6 dBm. The receiver achieves a conversion gain of 8.1 dB with an IIP3 of -13.74 dBm.
In this paper, detailed analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET are described. The FinFET with narrow fin width such as below 30 nm is attractive for scaled CMOS because of double gate structure. Additionally, the flicker noise of FinFET decreases and the temperature dependence of the noise become smaller as the fin width becomes narrower. According to our...
This paper presents a detailed analysis of latch-up characteristics for 90 nm RF CMOS on high-resistivity substrate with 400 ohm-cm for the first time. According to our measurement and simulation results, latch-up dependence of PNP base and NPN emitter injection mode on Si substrate resistivity is small. On the other hand, PNP emitter and NPN base injection modes are sensitive to the resistivity because...
This paper describes a low phase noise low dc power quadrature voltage controlled oscillator (QVCO) with a reflection-type IQ modulator. The QVCO using a standard bulk 0.18-mum CMOS process achieves a low phase noise of -115 dBc/Hz at 1-MHz offset frequency, a figure of merit (FOM) of - 191 dBc/Hz, and a core dc power consumption of 5.8 mW with a supply voltage of 1.8 V. The tuning frequency of the...
A 60 GHz I-Q VCO covering the frequency range from 57.5 to 63.1 GHz is presented. It exhibits a phase noise of - 95.3 dBc/Hz at 1 MHz offset from a 57.5 GHz carrier. Fabricated in a 65 nm bulk CMOS process, the two VCO-cores consume 30 mA in total from a 1.2 V supply.
To satisfy consumer demand for ultrahigh-speed wireless communication, voltage controlled oscillators (VCOs) in the D-band using CMOS as well as compound semiconductors are under development. However, the tuning range of such oscillators is limited by the small-size of the varactors. In this paper, a 115 GHz CMOS VCO with a 4.4% tuning range is proposed. To improve the tuning range of the VCO, the...
This paper presents a low phase noise quadrature ring oscillator with new start-up circuit. The oscillator architecture is two-stage differential ring with additional pair of transition-assistance inverters. The circuit was implemented in 0.18 mum CMOS technology and the measured tuning range of the prototype device is from 1.7 GHz to 5.5 GHz and figure of merit (FOM) is -162 dB. The proposed area...
Pseudo-millimeter-wave 12 times CMOS frequency multiplier has been proposed, which is attractive to overcome the drawback of using PLL circuit in the point of large power consumption and large chip area. To realize pseudo-millimeter-wave UWB communication, early work has been improved to overcome the limitation of operating speed. Short pulse injection and nonlinearity of PMOSFET have been used for...
This paper presents a comparison of two low-noise mixers designed in Infineon's 0.13 mum CMOS and 0.35 mum SiGe:C processes. The mixers have been optimized for low-noise performance for narrow-band 24 GHz applications. Both circuits are based on the Gilbert cell and have similar topology. The chips are designed to fulfill high robustness requirements for industrial and automotive applications. The...
This paper investigates the advantages of using PMOS devices for passive resistive mixer design. The experimental results presented in this paper demonstrate that PMOS mixers offer the advantage of higher signal to noise ratio at very low output frequencies. The significantly lower 1/f noise more than compensates for the higher conversion loss on PMOS mixer as compared to the NMOS mixer. The PMOS...
This paper reports a new Dynamic Threshold Voltage MOS (DT-MOS) transistor using foundry 90-nm CMOS process. Adopting the sub-circuit of the source follower, the proposed device could be operated in the voltage over 0.7 V. Measurement results demonstrate the 33% improvement of current driving capability and 20% improvement of transconductance compared to the reference MOS transistor. Moreover, the...
A 24-GHz single-pole double-throw (SPDT) transmit/receive switch fabricated in the 0.18-mum CMOS process is presented. The T/R switch is designed to improve the isolation and power handling capability by shunt inductor resonance and body-floating techniques. On-wafer measurement of the switch is performed. The 24-GHz switch exhibits the return losses at all ports of higher than 14 dB, insertion loss...
A fully differential 60 GHz down-converter in 65-nm CMOS technology is presented. The circuit, including the buffers, draws 5 mA from a 1.2 V supply. The measured power conversion gain is 4 dB with an IF 3 dB bandwidth of 1.3 GHz. Measured IIP2 and IIP3 are 16.6 and -6 dBm respectively. The mixer will be part of a 60 GHz receiver.
A fully integrated 2.4 GHz CMOS RF transceiver with short range wake-up function for low-rate wireless personal area network (LR_WPAN) applications in a 0.18-mum CMOS technology is implemented and measured. The chip fully complies with the IEEE 802.15.4 standard. The single chip transceiver incorporates an I/Q modulator and demodulator, an integrated RF synthesizer with a stacked voltage controlled...
This paper presents a 10-Gb/s coherent detection system incorporating feed-forward equalizers (FFEs) and an optical duobinary modulation scheme in order to increase the transmission distance limited by chromatic dispersion in standard single-mode fibers up to 400-km without signal regeneration and optical dispersion compensation. The FFE structure is based on a finite impulse response (FIR) filter...
A method based on equivalent circuit is presented to design a class of compacted millimeter wave bandpass filters in standard 0.18-mum CMOS process. Thin film microstrip is properly constructed on the lossy silicon substrate to realize small insertion loss. Using broadside-coupled scheme, thin film microstrip bandpass filters are designed and fabricated. Equivalent circuit model and theoretical network...
A 2.4/3.4 GHz dual-band CMOS power amplifier using proposed variable inductor is presented. The variable inductor is used for the load of driver amplifier stage. The measured P1 dB and PAE of dual band PA is 22.4 dBm and 28.8% at 2.4 GHz, and 18.8 dBm and 14.4% at 3.4 GHz, respectively. Also the measured output power at which the achieved EVM is -25 dB is 15 dBm at 2.4 GHz and 12.7 dBm at 3.4 GHz...
This paper proposes novel dual-band matching network, suitable for the design of integrated concurrent dual band power amplifier in a multi-standard radiofrequency frontend. The effectiveness of the proposed dual band matching network was demonstrated through the implementation of a power amplifier operating at 2.4 GHz and 3.5 GHz in IBM 0.13 mum CMOS technology. The designed 1.25 mm times 1.25 mm...
A large down-conversion of the carrier signal is required in a millimeter-wave receiver. However, since a steep filter in the millimeter-wave band is not available, a heterodyne architecture is commonly used, which increases the power consumption of the receiver. To realize low-power consumption in a millimeter-wave receiver, low intermediate frequency conversion is suitable but requires a millimeter-wave...
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