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On-wafer measurement setups are introduced for measuring the noise figure and s-parameters of differential 60GHz circuits. The need for expensive four-port mm-wave vector network analyzers is circumvented by using magic-Ts, providing a minimum CMRR of 20dB, in combination with cheaper two-port mm-wave network analyzers. Waveguide interfaces are used in the vicinity of the RF probes to achieve a robust...
This paper presents a two-stage fully integrated 60 GHz differential Low Noise Amplifier implemented in a TSMC bulk CMOS 65 nm technology. Implementation of a voltage-voltage feedback enables the neutralization of the Miller capacitance and the achievement of flat gain with a deviation of ?? 0.25 dB over the entire 6 GHz bandwidth. It features a transducer gain (Gt) of 10 dB along with a noise figure...
A 60 GHz I-Q VCO covering the frequency range from 57.5 to 63.1 GHz is presented. It exhibits a phase noise of - 95.3 dBc/Hz at 1 MHz offset from a 57.5 GHz carrier. Fabricated in a 65 nm bulk CMOS process, the two VCO-cores consume 30 mA in total from a 1.2 V supply.
A fully differential 60 GHz down-converter in 65-nm CMOS technology is presented. The circuit, including the buffers, draws 5 mA from a 1.2 V supply. The measured power conversion gain is 4 dB with an IF 3 dB bandwidth of 1.3 GHz. Measured IIP2 and IIP3 are 16.6 and -6 dBm respectively. The mixer will be part of a 60 GHz receiver.
This paper presents a 60 GHz voltage controlled oscillator implemented in conventional 65 nm CMOS technology. This VCO employs an alternative tuning system based on the Miller capacitance instead of conventional varactors. The presented VCO has a tuning range of 10.5 % and operates in the frequency range of 59.5 GHz to 66.1 GHz. It has an output power of -13 dBm and a phase noise of 80 dBc to -85...
This paper presents two monolithic transformer structures exhibiting high self resonance frequencies(fSR). Effect of positive and negative coupling factor on self resonance frequency is investigated. The transformer turn ratio and structure is selected to improve design and ease layout of a high frequency LNA and VCO. Measurement results of a transformer show good agreement with simulated values and...
A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is...
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