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An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2) films is presented during direct tunneling (DT) of electrons at -1.8 V of gate bias. The measurement results can be best explained by hole generation via anode hole injection (AHI) mechanism and the subsequent trapping of holes in the as-fabricated neutral hole traps in the oxide. A comparative study...
Composition of the silicon-nitride charge trap layer strongly impacts electron and hole trap properties. This significantly impacts charge trap flash memory performance and reliability. Important trade-offs between program/erase (P/E) levels (memory window) and retention loss is shown and critical trends identified. Increasing the Si-richness of the SiN layer improves memory window by increasing erase...
This paper reviews recent advances in Charge Trap Flash (CTF) memories. CTFs are predicted to replace the traditional floating-gate flash devices beyond the 32 nm node. The paper focuses on work done at IIT Bombay in the areas of both nitride-based SONOS devices as well as nanocrystal (NC)-based devices. For SONOS devices, results are presented for optimization of the nitride layer to obtain the best...
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