The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
With the rapid development of integrated circuit industry, the demand for low voltage operation and high speed of digital CMOS circuits is becoming inevitable. The Dynamic Threshold voltage (DT) technique emerged to extend lower bound of power supply, while the strained silicon technique stands out as a cost-effective way to improve circuit speed. In this work, the combination of Dynamic Threshold...
Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process, the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and reliability. Even for ideal strained Si on SOI substrates, the impacts of various CMOS process steps, e.g., patterning, oxidation,...
In this paper, an accurate and efficient one dimensional self-consistent numerical solution of <100> uniaxially strained n-MOS structure is presented based on finite element method. The solution is developed using FEMLAB considering wave function penetration effect into gate oxide. Significant change occurs in the eigen energies and the electron occupancies, intrinsic carrier concentration,...
This paper provides an overview of metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, i.e., extremely low source/drain resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of...
Schottky barrier MOSFETs (SBTs) have attracted much attention as a candidate for achieving high-performance in future ULSIs. Their potential advantages are low electrode resistance, short channel effect immunity and high carrier injection velocity, and many more. The major obstacle is however, to reduce the Schottky barrier height (??b) in these devices (both n- and pMOSFETs) since large ??b severely...
A systematic study of the Schottky barrier lowering induced by dopant segregation during Ni and Pt germanidation is presented. Both investigated doping species, As and P, segregated at the germanide/Ge interface during germanidation due to the snowplow effect. The effective Schottky-barrier height at 0 K of NiGe/n-Ge reduced from 0.72 eV for diodes without ion implantation to 0.19 eV by As segregation...
P-type Schottky barrier nanowire transistors (p-SB-NWTs) are computational studied in this paper. We analyzed the working principle and physical limits on their performance in details. The impact of Schottky contact of SB-NWTs on the current drivability, gate control and RF performance are studied comparing with conventional silicon nanowire transistors (SNWTs). It is pointed out that the inferior...
The performance of the n-channel Schottky barrier MOSFET with asymmetric barrier height at source/drain (A-SBFET) was numerically simulated. The impact factors on the performance are studied. The results suggest the on-state characteristics of the devices are mainly determined by the source-side barrier height (SBH). Increasing SBH or decreasing body thickness can optimize the sub-threshold slope,...
Reduced Bulk Field (REBULF) technology is used in the design of lateral power devices to improve breakdown voltage. Since this technology was firstly presented in 2006, this technology has gained widespread attention amongst researchers and has shown to offer good performance in a variety of application domains, especially in bulk silicon and SOI. This paper aims to offer a compendious and timely...
A new emitter layout in SiGe HBT is presented to improve the thermal stability. For comparison, a SiGe HBT with conventional layout is also fabricated. The thermal resistance and I-V characteristics of two types of HBTs at different biases and ambient temperature are measured and compared. Experimental results show that the new emitter layout is very effective in enhancing thermal stability over a...
In High Voltage Transistor (HVT), device characteristics could be affected by little changes of doping concentration or parasitic charges due to low substrate doping concentrations. Humps caused by boron segregation in sub-threshold region of HVT make bad effects on device characteristics. In this paper, we have presented the novel Fermi Level Controlled HVT (FCHVT) to simply eliminate hump effects.
High-voltage PMOS (HV-PMOS) with field-oxide as gate dielectrics for scan driver chip of plasma display panels (PDP) is disclosed in the paper, which is based on the epitaxial Bipolar-CMOS-DMOS (BCD) process. The key considerations during the design are proposed here, and abundance simulation and process regulation is done on the structure and parameter optimization, by the testing on the HV-PMOS...
A novel type of p+(SiGeC)-n--n+ diodes with ultra fast and ultra soft reverse recovery characteristics is presented. The improvement of the novel diodes is achieved by the combination of new device structure and new semiconductor material. Based on the introduction of `ideal ohmic contact??, the softness factor increases over four times, the reverse recovery time is over 60% short and the reverse...
A new SOI LIGBT structure with a combination of uniform and variation in lateral doping profiles on partial membrane (UVLD PM SOI LIGBT) is proposed in this paper. Its silicon substrate under the drift region is selectively etched to remove the charge beneath the buried oxide so that the potential lines can release below the membrane, resulting in an enhanced breakdown voltage. Moreover, combining...
In this paper, a novel power device named as RESURF Dielectric Inserted (REDI) LDMOS is put forward. It is fully compatible with standard CMOS technology, which can sharply reduce the cost. In this novel REDI LDMOS, a RESURF structure and a dielectric region are inserted at the suitable position of the drift region to reconstruct the electric field and the electric potential distributions of the channel...
In this paper, focused on especial requirement of monolithic power IC, a BCD compatible technology was studied and built up by solving a series of key technical issues. Using the BCD process, NPN, N-type VDMOS, PMOS, NMOS devices are obtained. For NPN transistor, BVCEO is 25 V and ?? is 50, for N-type VDMOS transistor, BVDS is 35 V and VT is 2.5 V, for PMOS transistor, BVDS is 15 V, and VT is -1.5...
In this paper, the 2nd LEDMOS devices based on bulk silicon(BS) process for an advanced PDP data driver IC have been developed. Not only the on-state characteristics, but also the reliabilities of 2nd LEDMOS transistors such as hot carrier effect, Kirk effect issues are improved against the 1st LEDMOS. The devices can be realized by shrinking the cell size and partly changing the structure of the...
The improvement of on-state resistance with partially slotted STI (shallow trench isolation) for medium voltage power devices in an advanced 0.25 um BiCMOS-DMOS process is implemented. Experiment results show that our proposed device can reduce 20% RON without hurting breakdown voltage. The partially slotted STI structure avoids breakdown voltage to decrease and also shortens the drain current path...
The design of Si/SiGe HBT for high-frequency microwave power amplification was presented in this paper. The material profile structure of the device was designed. A comb liked structure with 6-fingered emitter was employed for the SiGe HBT. Then the device was fabricated by using the buried metal self-aligned double mesa process and high resistivity substrate in a 3 ??m manufacture process line. The...
The microelectronics industry is facing historical challenges to down scale CMOS devices through the demand for low voltage, low power and high performance. The implementation of new materials and devices architectures will be necessary. HiK gate dielectric and metal gate are among the most strategic options to implement for power consumption and low supply voltage management. Multigate architectures...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.