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Mobility enhancement by strain is a critical element in today??s CMOS technology, and enables continued performance scaling. By modulating fundamental material properties, various strained Si techniques boost device and circuit performance independent of geometric and power supply scaling. Challenges for strained Si in aggressively scaled technology demand new ideas and materials.
This paper provides an overview of metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, i.e., extremely low source/drain resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of...
The performance of the n-channel Schottky barrier MOSFET with asymmetric barrier height at source/drain (A-SBFET) was numerically simulated. The impact factors on the performance are studied. The results suggest the on-state characteristics of the devices are mainly determined by the source-side barrier height (SBH). Increasing SBH or decreasing body thickness can optimize the sub-threshold slope,...
The design of Si/SiGe HBT for high-frequency microwave power amplification was presented in this paper. The material profile structure of the device was designed. A comb liked structure with 6-fingered emitter was employed for the SiGe HBT. Then the device was fabricated by using the buried metal self-aligned double mesa process and high resistivity substrate in a 3 ??m manufacture process line. The...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
This paper presents a MOSFET scaling study based on the current 45 nm technology generation. The study is based on a real 35 nm gate length design, to which the simulation tools are carefully calibrates. Features such as strain enhancement, and high-?? / metal gates are included in the simulations, which then exhibit equivalent performance to state-of-the-art bulk devices. Realistic choices of device...
Negative bias temperature instability (NBTI) in PMOS has emerged as one of the critical reliability concerns in deep sub-micron devices. A comprehensive study has performed to improve the device NBTI performance by process optimization. It is found that the most effective ways to reduce the NBTI degradation are to control the nitrogen concentration and profile in the nitrided gate oxide, to implement...
LaAlOx with a permittivity of 17 is fabricated successfully by ALD method. Enhanced deposition rate, improved uniformity and self-limiting behavior were observed for LaAlOx compare to La2O3 deposition. The mechanism behind improvement is proposed. ALD LaAlOx is found to be thermally stable up to 850??C anneal. Compared with Al2O3 blocking oxide control samples, the SONOS devices with LaAlOx blocking...
A nonvolatile static random access memory (NVSRAM) cell with two back-up CuxO memory devices is proposed in this paper. The manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme, the proposed cell can work correctly in four different operation modes. Compared with the standard SRAM cell, the proposed cell offers non-volatile storage which allows...
In this paper, the characteristics and mechanism of the transition metal oxide (TMO) based resistive switching memory (RRAM) devices were addressed. The results show that doping in oxide matrix materials, electrode material, and operating mode of the set/reset process may significantly affect the resistive switching behaviors of RRAM devices. Optimizing the dopants and matrix materials, electrode...
Large current carrying capabilities of AlN/GaN/InN based heterostructures and high breakdown voltages make this materials system uniquely suited for applications in high power and/or high frequency electronic devices, including power amplifiers, broadband amplifiers, power switches, and radio frequency switches. AlGaN/GaN insulated gate transistors have additional advantages of extremely low leakage...
Performances of AlGaN/GaN HFETs have much improved recently and very high potential of this heterostructure for high power and high frequency electronic devices has been verified. Application of new device technologies such as field plate, recessed gate, digital pre-distortion circuit and dual field plate was essential to realize such high device performances both at 2 GHz, 5GHz and 26 GHz. However,...
This work reports, high electron mobility transistors (HEMTs) using a dilute antimony In0.2Ga0.8AsSb channel, grown by molecular beam epitaxy (MBE) system. Introducing the surfactant-like Sb atoms during growth of the InGaAs/GaAs quantum well (QW) was devised to effectively improve the channel confinement capability and the interfacial quality within the InGaAsSb/GaAs QW heterostructure, resulting...
This paper presents an overview of 65 nm poly gate fabrication challenges emerged during the device performance & yield enhancement on 300 mm wafer. The proposed solutions hinge on the improvement of some critical process parameters in 65 nm gate etch such as, critical dimension uniformity (CDU), through-pitch etch bias (TPEB), line width roughness (LWR) and poly gate profile. More than 7% yield...
This paper reports the comparison between conventional ash followed by wet bench process approach and the new all wet process for LDD implant application. The comparison covers the areas of defect performance, (material loss, electrical data, yield) and chemical consumption.
A new high compression compressor is proposed in this paper. This compressor has 7 inputs, 2 output, 2 carry-ins from adjacent two cells and 2 carry-outs to the next two cells. It achieves higher compression ratio than 4:2 compressor, 5:2 compressor and 6:2 compressor. Simulation shows that a 64x64 bit multiplier using this proposed 7:2 compressor is not only 16% faster than multiplier built with...
Advancement of field programmable gate array (FPGA) faces many challenges. Among the major ones are power management and high speed transceiver I/O demands. To overcome the challenges, process-design co-optimization is required. With co-optimization of process, circuit, and architecture, 45% static power reduction is achieved for a 40 nm FPGA design. With optimized analog devices, high data rate (8...
In this paper, the novel mechanical switch device: suspended-gate FET is applied to FPGA development. This device offers almost an ideal subthreshold swing and a hysteretic resistance switching, opening opportunities for low-power applications. The proposed device can be used as the building block of programmable elements and memory of an FPGA. Based on this device, the proposed FPGA architecture,...
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