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This paper provides an overview of metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, i.e., extremely low source/drain resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
An RF n-MOST model was developed based on PSP model, which is considered as one of standard surface potential based compact model for deep-submicron applications. The RF sub-circuit is presented after analyzing the structure and layout of a specific RF n-MOST, and the parasitic parameters extracted analytically. Validated in DC, AC small-signal, and large-signal analysis, it proves that an excellent...
This work is referring to the nMOSFET singer-finger, multi-finger structures under the Electro-Static Discharge (ESD) zapping, and to evaluate the current distribution situations. By using the TCAD and HSpice, because of the internal parasitic resistance differences in each one finger, which can cause non-uniform turned on. Meanwhile, with different interior parasitic capacitor on each nMOSFET type,...
We present a historic overview of the initial motivating ideas, original foundations, and subsequent development, of integration-based methods which are currently used to extract semiconductor device model parameters, as well as to assess devices?? and circuits?? non- linearity. To illustrate these methods?? capabilities, in this paper we review sample applications specifically focusing on two-terminal...
A simple procedure to determine source/drain series resistance and effective channel length has been developed for advanced MOSFETs operated in linear region. The gate-bias dependence of source/drain resistance is considered. This new-developed procedure has been applied to devices with mask channel lengths of 0.23, 0.2, and 0.185 ??m. The parameters extracted with this procedure have been validated...
We fabricated a carbon nanotube (CNT) via interconnect and evaluated its electrical properties. We found that the CNT via resistance was independent of temperatures, which suggests that the carrier transport is ballistic. From the via height dependence of the resistance, the electron mean free path was estimated to be about 80 nm, which is similar to the via height predicted for hp32-nm technology...
Practical aspects of synthesis and applications of single-wall and multi-wall carbon nanotubes (SWNT and MWNT, respectively) are presented. Among numerous potential applications, utilization of nanotubes for interconnections in microelectronics and in gas sensors is considered in more detail. The issues related to compatibility of nanotubes synthesis and manipulation processes with the Si planar technology...
We report on the experimental evidence of a fully ballistic nano-FET with a voltage gain higher than 1 which is based on a 1D quantum ballistic conductor. In such a FET, the transconductance and the output conductance are basically modulated by the 1D subbands and the experimental results can theoretically be explained based on the Landauer-Buttiker formalism and the Buttiker model of the saddle-point...
Low resistance Ti/Al/Ni/Au Ohmic contact to (NH4)2Sx treated n-type GaN has been studied in the temperature range from 25??C to 600??C It is found that the specific contact resistivity ??c of the sample treated with (NH4)2Sx solution for 5 min at 90??C decreases with increasing measuring temperature, while the ??c of the sample treated with (NH4)2Sx solution for 25 min at 90??C increases with increasing...
A nonvolatile static random access memory (NVSRAM) cell with two back-up CuxO memory devices is proposed in this paper. The manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme, the proposed cell can work correctly in four different operation modes. Compared with the standard SRAM cell, the proposed cell offers non-volatile storage which allows...
SRAM, the important memory component, has been widely used in design of digital and communication circuits. SRAM is also an effective vehicle for process development and qualification due to its complexity and high density in which an engineer is able to detect the process issues. Generally SRAM??s yield is used as an indicator of the semiconductor nodes yield. In this paper we present the analysis...
This paper shows that that H plays a role in the forming of oxide RRAM which is derived from studies of both the electrical and physical properties of the oxides. Going forward, there is a clear need for additional studies that combine careful physical and electrical characterization of oxide and sulfide RRAM devices, as electrical measurements alone are ambiguous. If a thorough understanding of the...
Scalable elements that can be switched between widely-separated non-volatile resistance states at very low power are desirable for applications in next generation memory and logic. One promising approach involves the use of solid ion-conducting films. A mobile metal ion-containing glassy electrolyte film sandwiched between an oxidizable metal layer and an inert electrode constitutes a device which...
The resistance switching characteristics of several metal oxides has been reported recently for nonvolatile memory applications (NVM). However, various issues such as the switching mechanisms, switching uniformity, scalability and reproducibility have not yet been solved. In this paper, we discuss the recent progress of switching mechanisms and switching behaviors of various materials.
Excellent nonpolar resistive switching behavior is reported in the Cu doped ZrO2 memory devices with the sandwiched structure of Cu/ZrO2:Cu/Pt. The ratio between the high and low resistance is in the order of 106. Set and Reset operation in voltage pulse mode can be as fast as 50 ns and 100 ns, respectively. Multilevel storage is considered feasible due to the dependence of ON-state resistance on...
Recent advances of a highly scalable bridge phase change memory cell are presented. To fabricate and characterize highly scaled devices, designs in both the process procedure and the testing algorism are considered extensively. We also compare the characteristics of the devices made from different types of materials. The experimental data reveal the superior scaling properties of the bridge phase...
We present recent studies on amorphous silicon (a-Si) based resistive switching nonvolatile memory devices. The devices exhibit excellent performance of high on/off resistance ratio, high yield, fast speed, long retention/endurance and are fully compatible with CMOS processing. High-density crossbar arrays were successfully demonstrated without degradation of the device performance as compared to...
In this paper, the characteristics and mechanism of the transition metal oxide (TMO) based resistive switching memory (RRAM) devices were addressed. The results show that doping in oxide matrix materials, electrode material, and operating mode of the set/reset process may significantly affect the resistive switching behaviors of RRAM devices. Optimizing the dopants and matrix materials, electrode...
The resistive switching behavior of Ag/Si3N4/Pt device was observed and studied for the first time. Resistance ratio larger than 4*102 and 104s retention time were achieved which indicating its potential for resistive switching memory application. A physical model is proposed to explain the resistive switching behaviors of Ag/Si3N4/Pt devices.
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