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IC power consumption is not only a package thermal issue but also a significant and fast growing part of the world electricity consumption. A new low voltage transistor could contribute greatly to the need for a new Vdd scaling scenario. Green transistor (gFET) is based on tunneling and provides Ion and Ioff far superior to MOSFET at 0.2V if suitable low-Eg material is introduced into IC manufacturing.
RFID tags have gradually become popular tools for identification of products. To ensure the secure information transaction of tags, a scheme of RFID system authentication protocol based on Elliptic Curve Cryptography (ECC) is proposed. However, hardware implementation of ECC processor for RFID tags is a challenge for the requirements of low-power consumption and low-cost chip resource. In the paper...
This paper describes the design and implementation of a reconfigurable low power 180-nm CMOS cascade Σ-Δ modulator for multi-standard wireless communication. Both architectural and circuital reconfiguration is used to adapt its performance to multi-standard applications. Post layout simulation reveals that the prototype achieves 86.82/54.88/66.51d B peak signal-to-(noise+distortion) ratio within bandwidth...
This paper describes a novel gate-level dual-threshold total power optimization methodology (GDTPOM) principle, which is based on the static timing analysis (STA) and total power consumption optimization techniques for designing high-speed low-power SOC applications using 90 nm MTCMOS technology. Based on the GDTPOM principle, a multiplier circuit, which has been designed using 90 nm MTCMOS technology,...
In large-scale system-on-chips (SoCs), the power consumption on the communication infrastructure should be minimized for reliable, feasible, and cost-efficient implementations. An energy-efficient network-on-chip (NoC) is necessary for application to high performance SoC design. Various low-power circuits are designed, and implemented in each open system interconnection layer. Low-swing serial link...
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