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Silicon MEMS as electrostatically levitated rotational gyroscope and 2D optical scanner, and wafer level packaged devices as integrated capacitive pressure sensor and MEMS swatch are described. MEMS which use non-silicon materials as diamond, CNT (carbon nano tube), LTCC with electrical feedthrough, SiC (silicon carbide) and LiNbO3 for multi-probe data storage, multi-column electron beam lithography...
Continuous device scaling has led to the development of various transistors such as Ultra-Thin-Body SOI MOSFET, FinFET, and gate all around (GAA) MOSFETs . As the device shrinks further, the ultimate MOSFET structure would be GAA nanowire MOSFET with a fully depleted channel thoroughly controlled by the gate electrode. In this paper, fabrication processes of silicon nanowire MOSFETs on bulk Si using...
In this paper, experimental studies on the carrier transport in silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is proposed, which takes into account...
The transport characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with radius of 5 nm have been investigated. Mobility was estimated by extracting of source/drain resistance.
In this work, channel thermal noise in the twin silicon nanowire MOSFET (TSNWFET) is predicted using analytic thermal noise model taking into account short channel effects. TSNWFET used in this work has 40 nm gate length, 5 nm radius of silicon wire, and the 3.5 nm of gate oxide. Predicted thermal noise is compared with that of the planar MOSFET using various processes.
This work studies the analog performance of uniaxially and biaxially strained single-gate fully depleted SOI nMOSFETs and standard and strained Si (sSOI) n-type triple-gate FinFETs with high-?? dielectrics and TiN gate material. The analysis is performed focusing on some important analog figures of merit such as transconductance, Early voltage, output conductance and intrinsic voltage gain. It is...
32 nm Si and Si1-xGex SOI Coplanar N Channel Vertical Dual Carrier Field Effect Transistors for mixed signal and communication applications are presented.
Mobility enhancement by strain is a critical element in today??s CMOS technology, and enables continued performance scaling. By modulating fundamental material properties, various strained Si techniques boost device and circuit performance independent of geometric and power supply scaling. Challenges for strained Si in aggressively scaled technology demand new ideas and materials.
The physical mechanisms of electron mobility (??e) enhancement by uniaxial stress are investigated for nMOSFETs with surface orientations of (100) and (110). From full band calculations, uniaxial-stress-induced split of conduction band edge (??EC) and effective mass change (??m*) are quantitatively evaluated. It is experimentally and theoretically demonstrated that the energy surface of 2-fold valleys...
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2 - 6 degree tilted off-axis (110) channel were reported. The transconductance of p-MOSFET with off-axis channel was significantly degraded compared with that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved compared with that of normal channel. The changes were larger than those observed...
With the rapid development of integrated circuit industry, the demand for low voltage operation and high speed of digital CMOS circuits is becoming inevitable. The Dynamic Threshold voltage (DT) technique emerged to extend lower bound of power supply, while the strained silicon technique stands out as a cost-effective way to improve circuit speed. In this work, the combination of Dynamic Threshold...
Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process, the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and reliability. Even for ideal strained Si on SOI substrates, the impacts of various CMOS process steps, e.g., patterning, oxidation,...
In this paper, an accurate and efficient one dimensional self-consistent numerical solution of <100> uniaxially strained n-MOS structure is presented based on finite element method. The solution is developed using FEMLAB considering wave function penetration effect into gate oxide. Significant change occurs in the eigen energies and the electron occupancies, intrinsic carrier concentration,...
Reduced Bulk Field (REBULF) technology is used in the design of lateral power devices to improve breakdown voltage. Since this technology was firstly presented in 2006, this technology has gained widespread attention amongst researchers and has shown to offer good performance in a variety of application domains, especially in bulk silicon and SOI. This paper aims to offer a compendious and timely...
A new SOI LIGBT structure with a combination of uniform and variation in lateral doping profiles on partial membrane (UVLD PM SOI LIGBT) is proposed in this paper. Its silicon substrate under the drift region is selectively etched to remove the charge beneath the buried oxide so that the potential lines can release below the membrane, resulting in an enhanced breakdown voltage. Moreover, combining...
The microelectronics industry is facing historical challenges to down scale CMOS devices through the demand for low voltage, low power and high performance. The implementation of new materials and devices architectures will be necessary. HiK gate dielectric and metal gate are among the most strategic options to implement for power consumption and low supply voltage management. Multigate architectures...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
A quasi two-dimensional conduction model based on the thermionic emission of charge carriers over the energy barriers at discrete grain boundaries is proposed. The grain boundaries are characterized by an energy-dispersed density of trap states and a conduction model is formulated for a polycrystalline silicon thin-film transistor with an intrinsic channel. A ??line?? charge is formed adjacent to...
Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying...
In this paper, a model of the effective mobility for the on-current of p-Si TFT is proposed, taking into account the gain size, the drain bias, the imperfection crystal scattering mechanism, and the surface-roughness scattering mechanism. It is found that at the linearity region, the effective mobility decreases with the drain bias increasing and increases with the grain size increasing. The simulation...
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