Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
MOSFET scaling has served our industry well for several decades by providing significant improvements in performance, density and power, but traditional MOSFET scaling has run into hard roadblocks. Interconnect and patterning technologies have also run into significant limitations when trying to follow traditional scaling methods. The past few years have seen the introduction of new materials and...
In this paper, focused on especial requirement of monolithic power IC, a BCD compatible technology was studied and built up by solving a series of key technical issues. Using the BCD process, NPN, N-type VDMOS, PMOS, NMOS devices are obtained. For NPN transistor, BVCEO is 25 V and ?? is 50, for N-type VDMOS transistor, BVDS is 35 V and VT is 2.5 V, for PMOS transistor, BVDS is 15 V, and VT is -1.5...
This work is referring to the nMOSFET singer-finger, multi-finger structures under the Electro-Static Discharge (ESD) zapping, and to evaluate the current distribution situations. By using the TCAD and HSpice, because of the internal parasitic resistance differences in each one finger, which can cause non-uniform turned on. Meanwhile, with different interior parasitic capacitor on each nMOSFET type,...
We demonstrated essential technological components for wafer-scale integrated CMOS nanotube circuits such as inverters, NAND, and NOR logic gates: 1.The full-wafer-scale synthesis and transfer of massively aligned carbon nanotubes, and device fabrication on 4 inch substrates 2. In-depth device study and tuning, and extensive doping study for the first wafer-scale integrated CMOS nanotube circuits...
300 mm silicon single crystals have been grown using 24-28?? hot zones with the aid of numerical simulation. Mechanical strength of silicon seeds has been tested and a new style seed chuck developed. The damage layers during cutting, double side grinding (DSG) and double side polishing (DSP) have been investigated. The processing technology and the defects in silicon based materials such as silicon...
The behavior of point defects within silicon can be changed significantly by controlling the chemical state at the surface. In ultrashallow junction applications for integrated circuits, such effects can be exploited to reduce transient enhanced diffusion, increase dopant activation, and reduce end-of-range damage.
Atomic Layer Deposition (ALD) has successfully been applied to advanced microelectronic applications importantly for conformal coatings on high aspect ratio devices. However, traditional ALD is limited in deposition rate because the ability to bring precursors rapidly to the surface. In this paper we review recent results for precursor delivery using advanced vaporization (Trijet) as well as recent...
Based on the 4-channels neural signal regeneration system which was realized by using discrete devices and successfully used for in-vivo experiments of rats and rabbits, an integrated circuit (IC) with 6-channels of neural signal regeneration has been designed and realized in CSMC??s 0.6 ??m CMOS technology. The IC consists of a neural signal amplifier with adjustable gain, a buffer stage, and a function...
In this study, an interface IC for capacitive accelerometer sensor was designed, was processed in 6 um standard bipolar process, and the IC operates in the supply voltage ranges ??6 V-??18 V. The IC consists of an active square wave generator, a symmetrical voltage reference, a low-capacitance high-impedance voltage buffer, demodulation block, pre-amplifier, self-testing module, etc. It can form a...
A module of genetic algorithms suitable for evolvement analog IC is designed, which don??t relate with specific physical circuits and has excellent transplant ability. With the help of the interface module, the module adapted well to evolvement analog filter circuits and wide band high gain amplifier etc to optimize their performance. Using SMIC 0.18 ??m CMOS mixed technology, a evolvement AGC amplifier...
How to apply watermarking techniques for IP protection in practice is now the most crucial and urgent problem in the field of IP protection. In this paper, a whole set of design approaches of watermarking systems for IP protection is firstly proposed, including design aim, evaluation indexes, basic framework, and general principles of selecting and designing watermarking models and watermarking algorithms...
This paper discusses an 8MHz square wave oscillator used for a clock signal of the digital core of a mixed signal integrated circuit (IC). The frequency is determined by a bias current that charges a capacitor until it triggers a comparator with a voltage reference as the second input. A low drop out (LDO) voltage regulator is used to supply the oscillator so that variations in the battery voltage...
Three-dimensional integrated circuit (3D IC) is emerging as an attractive option for overcoming the barriers in interconnect scaling, thereby offering an opportunity to continue performance improvements using CMOS technology. 3D IC offers the advantages of high performance, low power, smaller form-factor, and heterogeneous integration benefits. However, to enable the wide adoption of the 3D integration...
This paper presents a new symbolic methodology for the formal verification of high-level data-flow synthesis process. In the approach, high-level specification of a data-flow design is modeled with Kleene algebra with tests (KAT) as a relational expression. By analyzing this relational expression, assertions that establish properties of the high-level specification are obtained. Then, the problem...
In this paper, current micro electro mechanical systems (MEMS) technology and some inertial sensors will be discussed. MEMS technology is presently becoming a key technology for future microelectronics. Some remarkable developments in MEMS are the driving force behind the current MEMS field, and many MEMS devices in the market are using these technologies effectively. Some particularly remarkable...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.