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In this paper, an empirical truncated balanced realization (TBR) approach is introduced to reduce the model order of non-quasi-static (NQS) effects in MOSFETs. In the PSP model (an industrial standard in compact modeling of MOSFETs), a simple spline-collocation (SC) approach is most commonly used to compute NQS. The SC technique, however, suffers from relatively high computing effort. To the best...
We present a historic overview of the initial motivating ideas, original foundations, and subsequent development, of integration-based methods which are currently used to extract semiconductor device model parameters, as well as to assess devices?? and circuits?? non- linearity. To illustrate these methods?? capabilities, in this paper we review sample applications specifically focusing on two-terminal...
This article summarizes the history and progresses on our development of the Bipolar Field-Effect Transistor Theory (BiFET). The 2-Dimensional (2-D) rectangular geometry of the transistor (uniform in the width or Z-direction) is employed to decompose the 2-D equation into two 1-D equations which are parametrically coupled by the surface-electric-potential. This decomposition enables us to obtain the...
In this paper the propagation mechanism of new type ridged SiGe-OI optical waveguide has been analyzed. Using the numerical solution of effective refractive index, the effective refractive index of ridged SiGe-OI optical waveguide is calculated, and the ridged SiGe-OI optical waveguide structure parameters including the inter ridge height H, outer ridge height h, and ridge width W of waveguide are...
In this paper, we present the investigation of inverse narrow width effect (INWE) of 65 nm low-power process with dual gate oxide shapes. To evaluate the impact of STI process on narrow devices, we conducted different experiments in STI process steps, including STI liner, STI elevation, STI liner annealing and STI nitride pullback. The result shows only STI liner annealing and STI nitride pullback...
The traditional direct digital frequency synthesizer (DDFS) based on a lookup table has very high complexity. This paper describes a low complexity DDFS using smaller lookup table and with minimum additional hardware. The lookup table for sine/cosine functions is split into a coarse-precision ROM and a fine-precision ROM. Approximation of fine-precision ROM and application of shift registers are introduced...
A CMOS band-gap voltage reference with the characteristics of low offset and low supply voltage is presented in this paper. In order to reduce the effect of offset of operational amplifier, two feedback loops are introduced, so as to the factor of ??VBE is maximized meanwhile the factor of offset could be minimized. The area of layout is 1.5??1.3 mm2 with a 0.5 um CMOS process. Post-simulation results...
A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by...
The small signal transfer functions of a single-switch buck-boost converter are derived. This method relies on the three terminal PWM switch equivalent model. The frequency and time domain characteristics of the converter were got by using Matlab. The simulation results show that the system stability is ensured and the load effect is eliminated.
A voltage doubler, which avoids body effect and then improves rise time and efficiency even with 1 V power supply, is presented. This art is designed for word line boosting, using 0.18 um EEPROM technology. Not only the voltage doubler can work with capacitive load normally, but also it can supply load current and achieve higher efficiency. The whole circuit can be implemented on chip and is suitable...
This paper presents a novel application-dependent interconnect testing scheme for Xilinx FPGAs. In this scheme, the interconnects in FPGAs' application configuration (AC) are decomposed into line branches, and the targeted line branches are partitioned into multiple subsets so that the CLBs' test configurations required to test the line branches in each subset are compatible. Multiple test configurations...
The computational complexity and hardware design of block-matching criteria were discussed, and a novel MPDC algorithm and its VLSI structure for H.264 were presented, in which a QP adaptive MPDC threshold was derived from the basics of H.264 4??4 integer transform and 52-level scalar quantization and the calculation process was adjusted for hardware optimization. When QP is greater than 18, the proposed...
Model order reduction by truncated balanced realization (TBR) is better than Krylov subspace methods to achieve smaller models with global error control. TBR projects a system onto the dominant invariant subspace in terms of both controllability and observability measured by their gramians. However, to obtain two gramians, two Lyapunov equations have to be solved and its high computation costs involved...
Based on the equivalent Elmore delay model, a new delay model that takes inductance and thermal effect into consideration is presented in this paper. The proposed model with high efficiency has closed-form expression. Its solution exhibits high accuracy as compared to the other models. Simulation results show that the error in the propagation delay is less than 10% for RLC tree example.
This paper presents a new symbolic methodology for the formal verification of high-level data-flow synthesis process. In the approach, high-level specification of a data-flow design is modeled with Kleene algebra with tests (KAT) as a relational expression. By analyzing this relational expression, assertions that establish properties of the high-level specification are obtained. Then, the problem...
One-dimensional model is developed and solved numerically to investigate the flow of liquid and vapor in triangle grooves. The effect of liquid and vapor interfacial shear stress is taken into account in this model that can greatly improve the accuracy of the results. The results obtained from this simulation contain behaviors of pressure and flow patterns, the effect of different working conditions...
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