The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM...
Clustered superscalar is an attractive alternative to large monolithic superscalar, and point-to-point (p-to-p) network is often used as inter-cluster communication networks (ICCN) to transfer dependent values between clusters. This new class of networks has demands and characteristics different from traditional networks. In order to pursue high performance, it should be highly coupled with the microarchitecture...
The dead lock problem of conventional SAR DLL is discussed. Different improvement approaches to fix the dead lock problem of conventional SAR DLL are shown and compared. A new improved SAR controller whose relock-in steps are only 2 k is proposed in this paper. Its relock-in process is illustrated. Verification of this new SAR controller is done by Hspice simulation.
This paper presents a novel digitally controlled phase-locked loop (DCPLL) for SoC applications. The DCO of the DCPLL is designed by a flexible design method. By the method, a high performance of DCO can be implemented in a straightforward way. Finally, the DCPLL design is implemented by SMIC 0.18 ??m logic 1P6M CMOS technology. The area of the DCPLL is 0.08 mm2. The post-layout simulation results...
A kind of arithmetic and its implementation of bit-stream adder which can be used in digital signal processing were discussed in this paper. Compared with multi-bit adder, the bit-stream adder has the advantages of much simple structure and much small routing area. The ideal circuit model of the bit-stream adder was improved with a pipe line structure to make it work correctly in high frequency range...
A new high compression compressor is proposed in this paper. This compressor has 7 inputs, 2 output, 2 carry-ins from adjacent two cells and 2 carry-outs to the next two cells. It achieves higher compression ratio than 4:2 compressor, 5:2 compressor and 6:2 compressor. Simulation shows that a 64x64 bit multiplier using this proposed 7:2 compressor is not only 16% faster than multiplier built with...
Two novel structures for explicit-pulsed flip-flops are proposed in this paper. The charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures, and the short circuit power consumption is diminished by overcoming the race problem as well. Simulation results also indicate the new structures are ideal for high-speed and low-power digital...
A synthesis frequency inflexion phenomenon of VLSI synthesis process is discussed, and then a VLSI structural optimization method with its workflow based on the analysis of synthesis frequency infrexion and register insertion is proposed. Registers are usually used for sequential synchronization and increasing maximum operating frequency, but in this issue, they are utilized to avoid excessively high...
In this paper, the novel mechanical switch device: suspended-gate FET is applied to FPGA development. This device offers almost an ideal subthreshold swing and a hysteretic resistance switching, opening opportunities for low-power applications. The proposed device can be used as the building block of programmable elements and memory of an FPGA. Based on this device, the proposed FPGA architecture,...
This paper presents fully digital dedicated on-chip DLLs, allowing for synchronization of external and internal clocks in FPGAs. DLL clock delay compensation circuit, digital clock phase shifter, digital duty-cycle-correction circuit and clock divider. In a Smic 0.18 ??m CMOS process, its operation frequency range is 25 MHz~300 MHz at 1.8V. The peak-to-peak jitter is 35 ps. Dueing to the digital architecture...
In the paper, an FPGA (field-programmable-gate-array) based industrial Ethernet slave communication controller is proposed. The slave communication controller is compatible with a custom communication protocol and will be used in NC (numerical control) system. A distributed clock which is integrated in the slave controller and synchronizes to the system clock provides a precise time for each device...
This paper studies a new hold time failure mode found in deep sub-micron low power CMOS production scan testing. The root causes of failure are discovered and duplicated in simulations. Vccmin of scan chain integrity is defined and studied for the first time. Solutions for enhancing scan chain integrity are proposed.
With the increased use of FPGA in widespread applications, its?? size and speed has been rapidly increased, so more and more problems associated with performance defects are emerging. Performance defects such as delay defects will not lead to a functional fault, but will limit the frequency of the system. Only Stuck-at testing has not been sufficient to guarantee the reliability and quality, so testing...
A high-speed low-power programmable pulse-swallow divider is designed and fabricated in SMIC 0.18-??m CMOS process. Two critical paths that limit the operating frequency are analyzed. The proposed prescaler based on a shift-register-ring is insensitive to the Modulus Control (MC) during its first few input cycles, and thus wrong divide ratio caused by the MC??s delay can be avoided. The proposed pulse...
The conventional matched filter structures are investigated in this paper. An acquisition circuit based on the polyphase form matched filter in Global Positioning System (GPS) receiver is provided. At the cost of less hardware resource, the significant advantage in the speed of synchronization is offered. For 32??128 polyphase form matched filter, the critical path delay approximately reduces 1/2,...
The antenna effect is a phenomenon in the plasma-based nanometer processes that many charges are accumulated on metal wires which cause the degradation of gate-oxide. It also influences the chip reliability and manufacturing yield. Different with other methods based on Manhattan-architecture for the antenna avoidance, we propose the algorithm that combines jumper insertion and layer assignment (JILA)...
Based on the equivalent Elmore delay model, a new delay model that takes inductance and thermal effect into consideration is presented in this paper. The proposed model with high efficiency has closed-form expression. Its solution exhibits high accuracy as compared to the other models. Simulation results show that the error in the propagation delay is less than 10% for RLC tree example.
Multiple supply voltages (MSV) is a widely-used technology in low power VLSI designs. In MSV design, the voltage island is a crucial concern that the blocks with the same voltage level are clustered into one or more voltage islands to reduce the cost of voltage supply network and level converter. In traditional MSV design approaches, the high level synthesis and physical exploring iterate with each...
To eliminate hotspots in 3D designs, physical layouts are always adjusted by shifting hot blocks. However, these modifications may degrade the packing area as well as microprocessor performance greatly. Furthermore, to improve time-to-market via design cycle reduction, incremental design must move from an expert methodology to a mainstream design methodology: one that is automated, integrated, reliable,...
Implementation of floating-point arithmetic functions is an essential task in high-level synthesis (HLS). However, most of the existing HLS EDA tools cannot well synthesize floating-point functions. In this paper, we present an automatic method to implement general floating-point functions using piecewise polynomial approximation. Based on the proposed hardware architecture, our method achieves compact...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.