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This paper presents an overview of the electronic implementation of quantum-dot cellular automata (QCA). QCA is a computing paradigm that encodes and processes information by the position of individual electrons. This opens the possibility of dense, ultra-low power devices. Resent results are presented from QCA cells implemented using metal-dots, as well as investigations toward molecular and silicon...
A novel decoder for Complementary Code Keying (CCK) modulation is proposed in this work. Compared to the parallel decoder architecture based on Fast Walsh Transform (FWT), the presented pipelined architecture has better hardware sharing and utilization efficiency, as well as smaller area. Its hardware area for finding the maximum decoding output value is minimized by employing a low-complexity on-the-fly...
RFID tags have gradually become popular tools for identification of products. To ensure the secure information transaction of tags, a scheme of RFID system authentication protocol based on Elliptic Curve Cryptography (ECC) is proposed. However, hardware implementation of ECC processor for RFID tags is a challenge for the requirements of low-power consumption and low-cost chip resource. In the paper...
This paper presents a compact power efficiency model to be applied in the analysis and design of clock overlapping of four-phase Dickson charge pump. The hands in equations on the optimal clock overlapping are concluded. Based on 0.25 um CMOS technology, the proposed model is consistent with the simulation result. Both simulation and model validate the optimal clock overlapping range attains better...
A new delay line structure is proposed in this paper. The proposed delay line does not produce cumulative errors as a signal is transmitted along a conventional delay line. The application of the proposed delay line to the circuit design of FIR and IIR filter is described, and the simulation results of an IIR filter are presented.
This paper describes a low-noise low-offset CMOS readout circuit for MEMS capacitive accelerometers. It employs a feedback capacitance and a combination of switches to have the input parasitic capacitance and the offset voltage canceled. The raised current IDS of the input differential pair in the first stage is used to help reduce sharply the total low-frequency noises without increasing the complexity...
One 32-bit RISC processor for embedded application is presented. With respect to the limitation of power and area in the embedded system, the RISC processor is deliberately designed. Dual-issue technology is adopted to improve the performance; the complex logic of the dynamic scheduling algorithm is allocated into different pipeline stage to improve the frequency. Lower power design method is used...
The security processor proposed in this paper is composed by multiple cryptographic cores. And due to the use of embedded DMA and data burst transfer, the processor can act as a bus master. This architecture improves the efficiency of system bus and reduces the burden of host CPU. Additionally, the proposed processor is connected to the system bus via a GALS Wrapper. Thus, high throughput can be achieved...
The dead lock problem of conventional SAR DLL is discussed. Different improvement approaches to fix the dead lock problem of conventional SAR DLL are shown and compared. A new improved SAR controller whose relock-in steps are only 2 k is proposed in this paper. Its relock-in process is illustrated. Verification of this new SAR controller is done by Hspice simulation.
This paper presents a novel digitally controlled phase-locked loop (DCPLL) for SoC applications. The DCO of the DCPLL is designed by a flexible design method. By the method, a high performance of DCO can be implemented in a straightforward way. Finally, the DCPLL design is implemented by SMIC 0.18 ??m logic 1P6M CMOS technology. The area of the DCPLL is 0.08 mm2. The post-layout simulation results...
Two novel structures for explicit-pulsed flip-flops are proposed in this paper. The charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures, and the short circuit power consumption is diminished by overcoming the race problem as well. Simulation results also indicate the new structures are ideal for high-speed and low-power digital...
A synthesis frequency inflexion phenomenon of VLSI synthesis process is discussed, and then a VLSI structural optimization method with its workflow based on the analysis of synthesis frequency infrexion and register insertion is proposed. Registers are usually used for sequential synchronization and increasing maximum operating frequency, but in this issue, they are utilized to avoid excessively high...
A method to integrate custom layout with ASIC back-end flow for high performance datapath design is introduced in this paper. It combines custom physical design techniques with conventional standard-cell based timing-driven back-end design flow. The results of two subchip design cases using this method for datapath circuits and implemented based on Fujitsu 90 nm process are presented, achieving advantages...
An 8-bit 200 MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. The DNL/INL is 0.3/0.2 LSB according to MATLAB simulation results. This ADC is implemented in 0.5 um CMOS technology and the total power dissipation is merely 96 mW at a sampling rate of 200 MHz.
This paper describes a phase-locked loop (PLL) designed for clock multiplication. The PLL has a locking range from 10 MHz to 600 MHz at 1.8 V power supply. It has a very low peak-to-peak jitter which less than 50 ps at 150 MHz output frequency. It has been fabricated in a 0.18 ??m CMOS process. The area of the active layout of the PLL is 560 ??m * 400 ??m, and power consumption is about 6 mW.
Based on the preamplifier-latch theory, a new topology structure of ultra high-speed comparator with low offset voltage applied to ultra high-speed A/D converters, which is composed of a preamplifier that includes a positive and negative resistance connected in parallel as its load, a regenerative latch and a simple output stage, is proposed. The method to analyze the speed and input offset voltage...
A 12-bit 20 MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp...
This paper presents an improved latched comparator which is suitable for high speed folding and interpolation ADC. The proposed comparator minimizes the kick back noise while regenerates the analog input signals. Injection reducing switch is introduced to suppress clock feedthrough and charge injection error. Transistors in common-gate arrangement are inserted to reduce kick back noise. Simulated...
Bootstrapped switches are used in a variety of applications such as pipelined analog-to-digital converters and high voltage switches, and drivers. This paper proposes a novel bootstrapped switching scheme for rail-to-rail sampling circuit. The implemented switch using new scheme can sample full-spread (0-5 V) signals under 5 V supplies. The new switch well eliminates the standard CMOS bulk effect,...
A symmetrical charge pump circuit for DC-DC converters is presented in this paper. With a typical +12 V input achieved by high-voltage CMOS devices, the charge pump circuit can generate an output voltage higher than +30 V. The circuit is designed based on ASMC 0.35 μm BCD technology. The results show that the designed pumping circuit can drive a large current more efficiently, and the ripple voltage...
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