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This paper provides an overview of metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, i.e., extremely low source/drain resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
An RF n-MOST model was developed based on PSP model, which is considered as one of standard surface potential based compact model for deep-submicron applications. The RF sub-circuit is presented after analyzing the structure and layout of a specific RF n-MOST, and the parasitic parameters extracted analytically. Validated in DC, AC small-signal, and large-signal analysis, it proves that an excellent...
This work is referring to the nMOSFET singer-finger, multi-finger structures under the Electro-Static Discharge (ESD) zapping, and to evaluate the current distribution situations. By using the TCAD and HSpice, because of the internal parasitic resistance differences in each one finger, which can cause non-uniform turned on. Meanwhile, with different interior parasitic capacitor on each nMOSFET type,...
A simple procedure to determine source/drain series resistance and effective channel length has been developed for advanced MOSFETs operated in linear region. The gate-bias dependence of source/drain resistance is considered. This new-developed procedure has been applied to devices with mask channel lengths of 0.23, 0.2, and 0.185 ??m. The parameters extracted with this procedure have been validated...
We report on the experimental evidence of a fully ballistic nano-FET with a voltage gain higher than 1 which is based on a 1D quantum ballistic conductor. In such a FET, the transconductance and the output conductance are basically modulated by the 1D subbands and the experimental results can theoretically be explained based on the Landauer-Buttiker formalism and the Buttiker model of the saddle-point...
Low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with metal-replaced source and drain regions have been fabricated and characterized. Several technological schemes for replacing poly-Si with aluminum have been investigated and the relative merits of each are compared.
We present an overview and electrical results for a novel deep trench decoupling capacitor. The process of this decoupling capacitor borrows from the regular embedded DRAM trench process, but with significant process simplification for decoupling use which provide reduced cost and reduced process cycle time. This capacitor can provide significant chip-level area savings, using only 1/8 silicon real...
A 4 GS/s 2-bit non-time-interleaved flash ADC is designed for an IR-UWB (Impulse Radio Ultra Wide Band) receiver. In this flash ADC, implementing differential low-swing operation in analog part and CML (current mode logic) in digital part result in high-speed and low power consumption. Furthermore, because of the low-bit-sampling characteristic of the IR-UWB system, non-time-interleaved structure...
Based on the bulk driven PMOS transistor, a low voltage CMOS cascade current mirror (BDCCM) is presented, then the input/output impedance and frequency characteristics are discussed. Based on the simulation and test results of the TSMC 0.25 ??m 2P4M CMOS process, the minimal input voltage of BDCCM is about 0.3 V. Comparing BDCCM with gate driven cascade current mirror (GDCCM), the input/output linear...
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