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Dual stress liner process for high performance SOI CMOS technology at 32 nm technology node is improved through the use of dep-etch-dep, etch back, and spacer removal techniques. The stress benefit of DSL is preserved with improved gap fill for the manufacturing of sub-32 nm gate length transistors.
Integration of low-dielectric constant SiCOH dielectrics (k~3) adjacent to gate stacks is demonstrated using 65 nm technology. Substantial reductions in parasitic capacitances are achieved through reductions in the outer fringe component of the overlap capacitance and the capacitance between the gate stack and metal contacts. These results are consistent with modeling. Although this is demonstrated...
In this paper we present the first complex mixed-signal FinFET circuit (>1500 devices). Design and implementation aspects as well as measurement results of a 10-bit current- steering D/A converter are shown. The achieved performance proves the ability of recent FinEET technology to realize competitive mixed-signal circuits with large device count and wide range of device dimensions. Moreover the...
In the continuing thrust to extend Moorepsilas law, silicon is beginning to confront several issues that require innovative materials solutions to increase transistor and interconnect speeds while dealing with the increasing thermal loads of advanced microprocessors. The unsurpassed thermal, electrical and mechanical properties of diamond can be used to solve some of the thermal issues and enhance...
A new Si-on-AlN substrate has been fabricated and characterised both electrically and thermally. Thermal properties of the new substrate have been identified with a thermal resistance reduced by half to 47.5 K/W compared to reference SOI. Further improvements in fabrication of these new SOI substrates with regard to the alpha-Si layer, oxide layer and in AlN film quality itself would utillise the...
At zero-temperature-coefficient bias points, transistors are known to have stable DC performance with temperature variation. In this work, the RF behavior at those specific bias points is presented in order to provide design guidelines for low-power low-voltage circuits featuring stable RF performance in variable temperature environments and applications. Fully- and partially depleted SOI MOSFETs...
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