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Three topologies to globally distribute a clock signal in 3-D circuits have been evaluated. A 3-D test circuit, based on the MITLL 3-D IC manufacturing process, has been designed, fabricated, and measured and is shown to operate at 1.4 GHz. Clock skew measurements indicate that a topology that combines the symmetry of an H-tree on the second plane and local meshes on the other two planes will result...
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