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Many equalization techniques have been demonstrated for multi-Gb/s I/O transceivers in order to compensate for the limited bandwidth of the communication medium. Since the performance of links is typically defined by the bit-error-rate (BER), this paper proposes a new adaptation method using the BER as the objective function to maximize the receiver voltage margin. Measurement results compare the...
To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves performance for most channels. This is due to the...
A 2-tap DFE receiver, implemented in a standard digital 65 nm bulk CMOS process, is aggressively optimized for low power and area. The 0.22 mW/Gbps power/speed ratio of the receiver and core area of 30 mum times 40 mum are achieved by using a half-rate architecture, a sampling front end, soft-decision direct feedback equalization and rail-to-rail CMOS clocking. At 11 Gb/s (2.6mA from 0.9V supply),...
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