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A new surface potential based poly-Si TFT model for circuit simulation was developed, accounting for the influence of both deep and tail states across the band gap. The model describes the drain current for all regions of operation using the unified equation. Calculations using the drain current model produce results that are in good agreement with the measured I-V characteristics of poly-Si TFTs
We present a new, PSP-based compact model for symmetric 3-terminal FinFETs with thin undoped or lightly doped body, which is suitable for digital, analog, and RF circuit simulation. The model is surface potential based and is demonstrated to accurately describe both TCAD data and measured FinFET currents, conductances, and capacitances
This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k dielectric (k~2.5) with up to 9 Cu metal layers and 0.25/0.3/0.37mum2 SRAM cells. This platform also features an optional third gate oxide for either higher...
The paper developed a photodiode (PD) model for circuit simulation considering, contrary to existing models, the transient carrier generation explicitly in the solution of the continuity equation. The developed model is compatible with conventional compact electrical device models and is demonstrated to enable accurate simulation of opto-electronic integrated circuits. The electric field distribution...
Band structure of III-V material InSb thin films is calculated using empirical pseudopotential method (EPM). Contrary to the predictions by simple effective mass methods, our calculation predicts that the Gamma valley (with the smallest isotropic bulk effective mass) in InSb remains the lowest lying conduction valley despite size quantization effects in the presence of competing L and Delta valleys...
The authors report novel 1000degC-stable [Ir3Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good Phim-eff of 5.08 and 4.24 eV, low Vt of -0.10 and 0.18 V, high mobility of 84 and 217 cm2/Vs at 1.6 nm EOT, and small 85degC BTI <20 mV (10 MV/cm for 1 hr) are measured
A comprehensive exploration of how phonon scattering affects carbon nanotube FET is presented in this work. A full band electron and phonon Boltzmann transport equation (BTE) coupled with heat equation is used for the first time to asses the transistor performance. Comparing with measured data for the metallic tube, the importance of hot-phonon effect is shown. The model is then applied to explore...
Technology and characteristics of 8-mega density CMOS image sensor (CIS) with unit pixel size of 1.75times1.75mum2 are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced saturation capacity and ultra-low dark current have been obtained, which satisfy the requirements of high density digital still camera (DSC) application
In this work, the 1/f noise of the source follower (SF) in pinned-photodiode CMOS pixels is characterized. It is found that the 1/f noise in these pixels is actually due to a very limited number of traps and results in a random telegraph signal (RTS). It is pointed out how the correlated-double sampling (CDS) reacts on this RTS. The temperature dependency of the imager read noise revealed two mechanisms...
Low temperature device operation at 240 - 300 K temperature range is a promising approach to extend the device technology. The guideline of device design for cooling CMOS and the optimum operation temperature considering total power consumption is discussed for the first time. Also, the compatibility of cooling CMOS with advanced high-k gate dielectrics and embedded SiGe S/D technique are clarified
A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current...
The formation of nickel silicide contacts in silicon nanowire transistors and its impact on the electrical device characteristics is investigated. The authors notice that silicide formation at low temperature converts substantial portions of the silicon wire into a metallic source/drain extension. The study also shows the impact of these contacts in a dual-gate field-effect transistor design and discusses...
A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., current and voltage) for the cell is significantly reduced by inserting a very thin Ta2O5 film between GeSbTe (GST) and a W plug. The Ta2O5 interfacial layer works not only as a heat insulator enabling effective heat generation in GST but also as an adhesion layer between GST and...
the authors report transport experiments on gate-all-around (GAA) TSNWFETs fabricated by top-down CMOS processes. The nanowire with 45 nm gate length exhibits single electron tunneling, and the total capacitance extracted from the measured data is in good agreement with the self-capacitance of an ideal cylinder. The nanowire with 125 nm gate length shows conductance quantization suggesting ballistic...
Thermoelectric effects enable direct energy conversion between heat and electricity. Various size effects can be explored to increase the thermoelectric performance of nanostructures compared to bulk. Boundary scattering reduces the phonon thermal conductivity, and quantum confinement and interface energy filtering can improve the electronic power factor. Theoretical and experimental results are described...
First demonstration of AC gain from a single-walled carbon nanotube transistor is presented. A top-gated carbon nanotube field-effect transistor (CNFET) is configured as a common-source amplifier and frequency response function of the amplifier is measured. Evidence of unambiguous signal amplification is observed in time domain as well as frequency domain up to a unity gain frequency of approximately...
A comprehensive study implementing a high-k/metal gate stack on Si(110) substrates has been performed, including a comparison of HfO2 and HfSiON, and compatibility with strain engineering. We demonstrate p-channel MOSFETs (pFETs) with optimized atomic layer deposited (ALD) HfO2 on Si(110) substrates with a ~ 3.3times high field hole mobility (μh) enhancement vs. a Si(100) substrate. On-state drain...
An effect of fluorine incorporation into HfSiON on 1/f noise is shown for the first time. Fluorine effect on 1/f noise for SiON and HfSiON devices differ in that F does not improve the HfSiON N-FET 1/f noise. Apparently, the interface traps created by Hf close to the conduction band cannot be passivated by fluorine. For future analog/mixed -signal applications, HfSiON P-FET is expected to limit noise...
We have investigated what effects randomly oriented and rotated poly-Si gate grains have on lateral carrier profiles in sub-50-nm MOSFETs by direct observations and electrical measurements. Since amorphous gates suppress random channeling penetration of pocket implants, we have increased effective mobility (40%), improved Vth roll-off characteristic (7 nm) and decreased Vth fluctuation (-26%)
The relationships between velocity, v, and mobility, μ, are investigated to clarify the effectiveness of μ enhancement to increase v in short channel FETs with SiO2 as well as high-K gate dielectric. The v-μ relationships were extracted on the basis of accurate understanding of v-μ dependence of μ; vsub dependences of μ in high-K, high Nsub, and short-channel FETs were carefully studied and the deviations...
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