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We present transistor and technology design considerations specific to low power applications from 90nm to 45nm and beyond. We discuss static power and low standby power (LSTP) transistors, and also touch on dynamic power dissipation and low operating power (LOP) transistors. As semiconductor transistor technology is encountering several intransigent limits (voltage scaling and overdrive, and gate...
Parasitic effects and Matthiessen's rule have been reinvestigated in the inversion layer mobility analysis. It is shown that an advanced split C-V technique newly developed is very useful for characterizing the intrinsic inversion layer mobility in short channel MOSFETs, even with very large parasitic effects. Furthermore, the validity of Matthiessen's rule is experimentally and theoretically investigated...
This paper presents a surface potential based poly-Si thin-film transistor (SPT) model for SPICE which is formulated with both surface and grain boundary (GB) potentials calculated by Poisson equations. The drain current model includes GB induced mobility modulation, hot carrier effect, gate induced drain leakage, and trap dependent thermal leakage. The capacitance model is derived from physically...
In this work the authors present, for the first time, an analytical noise modeling methodology in presence of lateral asymmetry. The authors also show that noise properties of lateral asymmetric (LA) MOSFETs are considerably different from the prediction of conventional Klaassen-Prins (KP) based methods and at low gate voltages; they can overestimate the noise by 2-3 orders of magnitude
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific...
Starting with the 45 nm node, a tradeoff between performance and density exists that become more severe at the 32 nm node. An in-depth analysis of the impact of pitch and increased parasitics on device performance in the 32 nm node is presented. To counteract these effects, reduction of parasitics, gate length scaling, and aggressive stress engineering are necessary. Optimized layout using a "relaxed-pitch"...
We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance...
SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product's lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (VT) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation...
We have investigated various doped metal oxides such as copper doped molybdenum oxide, copper doped Al2O3, copper doped ZrO2, aluminium doped ZnO, and CuxO for novel resistance memory applications. Compared with non-stoichiometric oxides (Nb2O5-x, ZrOx, SrTiOx), doped metal oxides show higher device yield. Moreover, Cu:MoOx have demonstrated excellent memory characteristics such as reliability under...
The performance of carbon nanotube field-effect transistors has been studied based on the non-equilibrium Green's function formalism. The effects of elastic and inelastic scattering and the impact of parameters, such as electron-phonon coupling strength and phonon energy, on the device performance are analyzed. The effect of scaling of the source-gate spacer, drain-gate spacer, and gate length is...
An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with < 100muA RESET current. The device concept provides for simplified scaling to small cross-sectional area (60nm2) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention
The feasibility of the charge-transfer based polymer resistive memory as a future data storage device was tested using a thermally robust polyimide and PCBM composite film, available by low-cost solution processing. The prototype device with a simple 4F cross-point cell structure demonstrated basic non-volatile memory functions (> 1000 write/erase cycles and 1-week data retention in an ambient...
GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity. p-TSNWFET shows high driving current of 1.94 mA/mum while n-TSNWFET shows on-current of 1.44 mA/mum. Merits of TSNWFET and performance enhancement of p-TSNWFET are explored using 3D and quantum simulation
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity...
64 Mb FRAM with a 1T1C scheme has progressed greatly for mass production in terms of a highly reliable device. For the first time, package-level reliabilities of the memory were evaluated systematically and massively. The authors scrutinized the device reliabilities in accelerated manners, one of which is high-temperature-operating-life (HTOL) test; and the other is high-temperature-storage (HTS)...
A novel Si MOS-LED is demonstrated, which is fully compatible with Si technology. It is based on a dislocation network fabricated by wafer direct bonding. Light emission at 1.5 μm was observed when the network was near the Si/SiO2 interface close to/inside the accumulation layer induced by the gate voltage
It is reported for the first time that the anomalous gate edge leakage current in NMOSFETs is caused by the lateral growth of Ni silicide toward the channel region, and this lateral growth is successfully suppressed by the control of the Ni silicidation region using the Si ion implantation (Si I.I.) technique. As a result, the anomalous gate edge leakage current is successfully reduced, and the standby...
In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy...
A thermo-mechanical stress model (TMS) is presented to explain the impact of sub-melt laser anneal (LA) on SiON dielectric and on the overall transistor performance. An Lgmin reduction of 15nm/5nm for nMOS/pMOS over our poly-Si/SiON reference, with 8% capacitance and 10% source and drain resistance (RSD) improvement, is demonstrated. Best device performance and NBTI immunity are reached by lowering...
In this work, using Si interface passivation layer (IPL) we present the electrical characteristics of TaN/HfO2/GaAs both p-and n-MOSFET made on GaAs substrates with excellent electrical and reliability characteristics, thin EOT (~2.3-3.0nm), low frequency dispersion (< 5%) and high maximum mobility (1213 cm2/V-s) with high temperature PMA for n-MOSFET on undoped GaAs. Good inversion behavior with...
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