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Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages were developed. The combination of a 50 mum EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. As a result, working imagers exhibiting...
We are exploring the feasibility of sequencing a single molecule of DNA using a revolutionary type of silicon integrated circuit that incorporates an on-chip nanopore mechanism with a molecular trap. The essential component is a single, nanometer-diameter pore in a robust, nanometer-thick membrane formed from a metal oxide semiconductor (MOS) capacitor. To sequence the molecule, the voltage induced...
Feasibility of high density probe-based memory with polycrystalline ferroelectric media has been demonstrated for next memory applications beyond sub-10 nm generation. Noble chemical-mechanical-polishing (CMP) method was employed to fabricate a very even surface on polycrystalline MOCVD Pb(Zr,Ti)O3 (PZT) media. On the CMP processed PZT media, domain dot array was able to be written and read even at...
A novel method to fabricate a transistor directly within a wire is presented. The phenomenon of aluminum-induced crystallization of silicon is used to embed crystalline Si regions within an aluminum wire, enabling FETs to be fabricated directly within interconnects. The wireFET fabrication process is relatively simple, does not require unconventional materials or processing methods, and has low associated...
This papers presents new results on silicon I-MOS devices, (where the source and the drain are doped of opposite type) obtained by an adaptation of a conventional CMOS process. Fabricated devices are fully functional down to 55nm of gate length, but the influence of the gate becomes strongly reduced for shorter devices due to technological limitations. Nevertheless, the smallest device, with a 17nm...
We report on a novel thermal select (TS) MRAM with multilevel programming capability. Exchange bias pinning of a magnetic free layer (FL) was used to achieve a thermally stable bit and to reduce writing currents. This report shows experimental data for a TS-based magnetic tunnel junction (MTJ) with a size of 50 times90 nm2, the smallest size reported so far. Multilevel capability with 2 bits per 1-transistor...
The paper describes a platform technology for three-dimensional (3-D) integration of multiple layers of silicon integrated circuits. The technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator devices hybridized with Si electronics. Among these applications are high performance infrared focal plane array detectors
A MOSFET structure called a FITMOS has been successfully developed that exhibits record-low loss in the 60V breakdown voltage range (Kasakian and Perrault, 2001). The device has a body diode with superior reverse recovery characteristics and exhibits an extremely small value for RonQgd. The distinctive features of this device are the use of floating P islands formed by self-alignment and trench gates...
This paper describes some of the most relevant challenges in the physically based modelling of transport in nano-MOSFETs. In particular, we start by discussing the determination of the band-structure in nano-scale devices. In fact, most of the device engineering options affect the device performance through the band-structure, which determines the carrier velocity and the scattering rates. We then...
CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6...
We report a normally-off GaN-based transistor using conductivity modulation, which we call GIT (gate injection transistor). This new device principle utilizes hole-injection from p-AlGaN to AlGaN/GaN heterojunction, which increases electron density in the depleted channel resulting in dramatic increase of the drain current owing to the conductivity modulation. The fabricated GIT exhibits the threshold...
We proposed a new termination structure to minimize the chip size of high breakdown voltage vertical DMOSFETs and to manufacture them using a MEMS process. As a result, we were able to realize a fully functional 1.7 mm square silicon DMOSFET with a breakdown voltage of 3200 V, a leakage current of 1.2 nA at 200 V and an on-state resistance of 165Omega
Record performance of a novel power transistor integrated in a 0.35 μm power IC technology is reported. Measured specific on-state resistance of 33 mOhm*mm2 for a 94 V breakdown is breaking the silicon-limit and is the lowest reported value to date. The device outperforms its nearest rival by a factor of 2.5. The device consists of the stacking of a vertical MOS on a fully depleted vertical drift...
The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss...
The superior characteristics of variable body-factor (γ) FD SOI MOSFETs which we have recently proposed are experimentally demonstrated. Devices were fabricated on a SOI wafer with BOX thickness of 10 nm by using the 140 nm technology. Their advantages, small leakage-current in the standby-state and improved delay in the active-state, are clearly validated by the measurements. This scheme is expected...
In this article, we proposed and successfully demonstrated 25 nm TiN metal gate nanorod transistors with laterally and vertically scaled actives without process burdens. They showed the excellent short channel effect immunity and high current drivability DIBLs are below 40 mV/V and subthreshold swings are nearly ideal values showing no temperature dependency. The driving currents of 1.4 mA/mum for...
The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step,...
ZnO or AlxGa1-xN charge trap device showed large memory window (>7V) with fast P/E speed (plusmn17 V, 100 (_is) and excellent retention (10-year memory window of 6 V with small charge loss rate; ~l/5 of that of Si3N4). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance...
High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps...
We report on the integration of sub-melt laser spike annealing (LSA) on W-gate stacked DRAM. We applied the LSA as a reactivation in back-end processes to comply with the considerable metal-pattern effects and strong DRAM thermal-budget. Improvements in drive currents of peripheral transistors (4 %/14 % for n/p-FETs) are achieved by using the LSA without incurring short channel effect (SCE) while...
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