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In this paper, different Hf-based oxides (HfO2, HfSiO under several annealing conditions, HfSiON, HfAlO with various compositions) are simultaneously considered as storage layers of charge-trap memories. Based on material characterization analyses, electrical data of memory cells, physical modeling of charge-trap devices, we show that a strict relationship exists between the crystal structure of the...
Low temperature device operation at 240 - 300 K temperature range is a promising approach to extend the device technology. The guideline of device design for cooling CMOS and the optimum operation temperature considering total power consumption is discussed for the first time. Also, the compatibility of cooling CMOS with advanced high-k gate dielectrics and embedded SiGe S/D technique are clarified
High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability....
If Si (110) channel can be used for both nMOS and pMOS FinFET, the implementation of FinFET can be simplified significantly. Electron mobility degradation at Si(110) channel of finFET has been one of the major barriers in this path. We report a creative method to improve electron and hole mobilities using a novel metal electrode induced-strain engineering, which also features the effective workfunction...
Frequency dependent charge pumping measurement has become an important tool for high-k dielectric reliability investigation. The interpretation of how deep the technique probes has become a controversy with important implication on the reliability of the high-k gate dielectric. The paper examines this problem experimentally and theoretically in this paper. Charge pumping experiment has been carried...
High-K dielectric gate stack MOSFETs have been characterized by separating the transversal and lateral electric field contributions to the substrate current. The results show that at low gate biases the substrate current is dominated by a trap-assisted tunneling component denoted by gate induced drain leakage (GIDL) current, which is not observed in conventional SiO2devices. Ultra-fast substrate current...
We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion Tox (Tinv) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and...
A dry etch process for metal/high-k stacks has been developed to solve the integration problems associated with wet etch removal of high-k dielectric from the source and drain (S/D) areas. An in-situ plasma (O2) treatment has been introduced for the first time to cure the damage induced by the high-k dry etch process. Excellent electrical performances, such as dramatically improved leakage current,...
We describe the low-field leakage through high-k interpoly dielectric stacks in floating gate nonvolatile memories with an inelastic trap-assisted tunneling model, which accounts for arbitrary trap distributions in both energy and space. A systematic investigation of the impact of trap parameters, stack composition, bias and temperature on the leakage is presented, focusing on Al2O3-based stacks....
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