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In this paper, different Hf-based oxides (HfO2, HfSiO under several annealing conditions, HfSiON, HfAlO with various compositions) are simultaneously considered as storage layers of charge-trap memories. Based on material characterization analyses, electrical data of memory cells, physical modeling of charge-trap devices, we show that a strict relationship exists between the crystal structure of the...
A comprehensive study implementing a high-k/metal gate stack on Si(110) substrates has been performed, including a comparison of HfO2 and HfSiON, and compatibility with strain engineering. We demonstrate p-channel MOSFETs (pFETs) with optimized atomic layer deposited (ALD) HfO2 on Si(110) substrates with a ~ 3.3times high field hole mobility (μh) enhancement vs. a Si(100) substrate. On-state drain...
We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET < 1.3 nm was...
This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO2 as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties. Reliability issues, stress and gate control in the sub-35nm...
High-K dielectric gate stack MOSFETs have been characterized by separating the transversal and lateral electric field contributions to the substrate current. The results show that at low gate biases the substrate current is dominated by a trap-assisted tunneling component denoted by gate induced drain leakage (GIDL) current, which is not observed in conventional SiO2devices. Ultra-fast substrate current...
A Si3N4/SiO2 double-tunneling layer is incorporated in a MONOS memory device structure with high-k HfO 2 charge storage layer for NAND-type memory application. Fast erasure of charges trapped in the high-k layer is enabled by enhanced hole current, accomplishing a large memory window of 2.9 V with electrical stress at 17.5 V for 100 (as and at -18 V for 5 ms. Incorporation of 1.6-1.8 nm thick Si3N...
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