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Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties...
High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability....
Feasibility of high density probe-based memory with polycrystalline ferroelectric media has been demonstrated for next memory applications beyond sub-10 nm generation. Noble chemical-mechanical-polishing (CMP) method was employed to fabricate a very even surface on polycrystalline MOCVD Pb(Zr,Ti)O3 (PZT) media. On the CMP processed PZT media, domain dot array was able to be written and read even at...
CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6...
In this article, we proposed and successfully demonstrated 25 nm TiN metal gate nanorod transistors with laterally and vertically scaled actives without process burdens. They showed the excellent short channel effect immunity and high current drivability DIBLs are below 40 mV/V and subthreshold swings are nearly ideal values showing no temperature dependency. The driving currents of 1.4 mA/mum for...
In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy...
HfO2high-K/TaN/TiN gate stacks n/p-MOSFETs have been studied. Ultrafast progressive breakdown (PBD) is polarity dependent and is found only in the case of substrate injection in metal gate n/p-MOSFETs. PBD transient of metal gate p-MOSFET is much slower than n-MOSFET in inversion mode stress
This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO2 as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties. Reliability issues, stress and gate control in the sub-35nm...
We have successfully developed the advanced FinFET fabrication processes for materializing FinFET CMOS circuits. Using the developed technologies, we demonstrate the advanced TiN metal gate, fin-height controlled FinFET CMOS inverter with an excellent transfer performance, and the flexible threshold voltage, asymmetric gate insulator thickness four-terminal (4T) FinFET with a greatly improved subthreshold...
For retention improvement in scaled SONOS-type nonvolatile memory, deep traps with controllable density were formed by adding metal impurities into gate oxide. We find that Ti additives create deep traps in silicon dioxide, with high electron capture efficiency Charge storage node changed from TiO2 floating-gate (15Aring) to nano-crystals (3Aring), and further to atomic-sized traps (0.4Aring) by decreasing...
We have successfully achieved high speed (~50 ns) unipolar operation in RRAM devices comprised of titanium oxynitride (TiON) combined with a control resistor connected in series. For unipolar switching, programming and erasing pulses can be the same width, typically, a few tens of nano-seconds. This enables high speed and high density cross-point RRAM memory arrays. In addition, we demonstrate how...
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