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Two integration schemes for hybrid crystal orientation technology using direct silicon bonded (DSB) substrates and solid phase epitaxy (SPE) processes have been implemented. The shallow-trench-isolation (STI) before SPE approach suffers from trench-edge defects formed at STI edges, which causes high leakage current. The SPE-before-STI approach allows removal of edge defects of SPE by STI. SRAM in...
This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k dielectric (k~2.5) with up to 9 Cu metal layers and 0.25/0.3/0.37mum2 SRAM cells. This platform also features an optional third gate oxide for either higher...
Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time 55-nm gate-length FinFET SRAMs with resist- and spacer-defined fins are electrically compared. Due to short-range process variations, SRAM bit-cells with spacer-defined fins show approximately 2.5 times higher variability in static-noise-margin...
We developed novel SRAM cells using bulk thyristor-RAM (BT-RAM). BT-RAM, formed on bulk Si wafers, is low cost and has good compatibility with logic process flows. BT-RAM has excellent performance, with a 100-ps read/write, high Ion/Ioff current ratio (> 108), and low standby current (< 0.5 nA/cell). We can expect the ideal cell size to be as low as 30 F2, one-fourth that of a conventional 6T-SRAM...
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific...
SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product's lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (VT) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation...
It is reported for the first time that the anomalous gate edge leakage current in NMOSFETs is caused by the lateral growth of Ni silicide toward the channel region, and this lateral growth is successfully suppressed by the control of the Ni silicidation region using the Si ion implantation (Si I.I.) technique. As a result, the anomalous gate edge leakage current is successfully reduced, and the standby...
The paper presents a comprehensive study of the impact of NBTI on SRAM Vccmin stability. The authors describe a novel simulation technique to predict the between - die statistical distribution of Vccmin drift due to NBTI. While the drift is a fundamental phenomenon, it was shown that by cell design and transistor process optimization, the drift can be reduced to tolerable levels
A nonvolatile SRAM cell with two back-up nonvolatile memory devices is proposed. This novel cell offers nonvolatile storage, thus allowing selected blocks of SRAM to be powered down during operation. There is no area penalty. A slight performance penalty is anticipated
For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (single-crystal Si layer stacking) technology, which was used to develop S3 SRAM previously. The NAND cell arrays are formed on the ILD as well as on the bulk to double the memory density without increasing the chip size. The feasibility of the technology was proven by the successful operation of 32...
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