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The authors present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS)/high-k dielectric and metal-in-collar (MIC), and low-k inter-level dielectric (ILD) are demonstrated
An aggressively scaled, self-aligned, independently controlled double-gate floating body cell (IDG FBC) is reported. This structure eases the scaling constraints of other FBC memory devices proposed to date. Enhanced memory performance has been demonstrated owing to the independent back gate with thin oxide and thin Si fin. Memory devices with 85-nm Lg and 30-nm fin widths (Z) have been shown to exhibit...
We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET < 1.3 nm was...
The authors present a 65nm embedded DRAM cell (0.127 μm2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided...
Feasibility of high density probe-based memory with polycrystalline ferroelectric media has been demonstrated for next memory applications beyond sub-10 nm generation. Noble chemical-mechanical-polishing (CMP) method was employed to fabricate a very even surface on polycrystalline MOCVD Pb(Zr,Ti)O3 (PZT) media. On the CMP processed PZT media, domain dot array was able to be written and read even at...
This papers presents new results on silicon I-MOS devices, (where the source and the drain are doped of opposite type) obtained by an adaptation of a conventional CMOS process. Fabricated devices are fully functional down to 55nm of gate length, but the influence of the gate becomes strongly reduced for shorter devices due to technological limitations. Nevertheless, the smallest device, with a 17nm...
The superior characteristics of variable body-factor (γ) FD SOI MOSFETs which we have recently proposed are experimentally demonstrated. Devices were fabricated on a SOI wafer with BOX thickness of 10 nm by using the 140 nm technology. Their advantages, small leakage-current in the standby-state and improved delay in the active-state, are clearly validated by the measurements. This scheme is expected...
In this article, we proposed and successfully demonstrated 25 nm TiN metal gate nanorod transistors with laterally and vertically scaled actives without process burdens. They showed the excellent short channel effect immunity and high current drivability DIBLs are below 40 mV/V and subthreshold swings are nearly ideal values showing no temperature dependency. The driving currents of 1.4 mA/mum for...
A novel technique in creating a cavity by using a membrane of Si-native oxide has been developed. The membrane of Si-native oxide was formed by high-selectivity Cl2 etching of Si which surface was treated by wet chemicals. Following film deposition onto the membrane which was supported by SiO2 mask can make a cavity in the substrate. The advantage of this technique is its ability to maintain the CD...
Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant
This study compares the RF power performance of 65 nm and 0.25 mum CMOS devices integrated on an advanced 65 nm process, and discusses their power and frequency limitations for the first time. The authors demonstrate output power levels of about 80 mW for 65 nm devices, and 450 mW for 0.25 mum devices when operated at their nominal voltages of 1.0 and 2.5 V respectively. The authors find that output...
A biological method for making the components of nano-electronic devices is proposed, which is named bio nano process (BNP). Using the BNP, the nanodot memory nodes of the floating gate memory were fabricated and excellent endurance and retention time were demonstrated
A state of the art Monte-Carlo simulator is applied to the investigation of the RF performance of bulk MOSFETs designed according to the prescriptions of the 2005 ITRS Roadmap for analog and mixed signal applications, and of a 53 nm ultra-thin-body (UTB) single-gate (SG) SOI MOSFET. We provide an analysis of the signal-delay build-up along the channel and an investigation of the scaling properties...
Results of statistical 3D Monte Carlo (MC) simulation of random dopant induced current variations are presented for a series of well-scaled nano-MOSFETs. Comparison is made with drift diffusion (DD) results showing an increase in the estimated current variation. This is associated with additional transport variation that has been included within the MC
This paper examines, by means of multi-subband-Monte-Carlo (MSMC) simulations, the prediction of the well known compact formula for back-scattering in nanoMOSFETs, analyzing the effect of carrier degeneracy and complex scattering mechanisms on the back-scattering. The paper also addresses the definition of an appropriate mean-free-path and its relationship to the low-field mobility
The advances in silicon technology that have been the backbone of tremendous previous growth, was foreseen in 1965 when Gordon Moore published his famous prediction about the constant growth rate of chip complexity. And, in fact, it has repeatedly been shown that the number of transistors integrated into silicon chips has indeed doubled every 18 months. Increases in packing density, according to Moore's...
Nanometer CMOS technology offers the required integration density for advanced products such as home theatre equipment and personal communication devices. The system solutions inside these products demand highly integrated systems-on-silicon, blending high-density digital functions with analog interface circuits. These integrated solutions have to cope with high data-rates, and thus require high speed...
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