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Base on the thermal-electric feedback network analysis, the thermal stability factor S is presented to express the thermal stability of the device. It is shown that the self-heating effect is compensated completely and the electrical characteristic of device won't shift when S=0. Furthermore, the expression of the minimum ballasting resistance R c of HBT to compensate the self-heating effect is presented...
After the shortage of the conventional lateral structure of SiGe HBT was analyzed, A new lateral structure was presented. In the meantime, the new fabrication process named buried metal self-aligned technique was designed. The measured frequency features show that the cut-off frequency fT of the device up to 12.3GHz and the maximum oscillation frequency fmax achieves 5.7GHz. Compared to the conventional...
A new method for realization of self-aligned lateral SiGe-HBT (SiGe-SLHBT) is introduced and ac and dc simulations are performed based on a two-dimensional physical model. The fabrication process is simple and requires a minimum number of masks. The details of the fabrication process have been discussed. Simulation results show a dc current gain of 658, fmax = 220 GHz,fT = 62.5 GHz and MSG = 32.1...
The polysilicon emitter bipolar process technology in which BF2-implanted base layer and rapid thermal anneal (RTA) are used has been reported. The process and device have been simulated by TSUPREM4 and MEDICI software respectively. High-speed NPN Transistor with beta of 160, fT of 9.5GHz and BVCEO of 6.0V has been achieved. Based on the NPN transistor, broad-band amplifier with bandwidth of 1.48GHz...
A new concept is proposed for improving characteristics of the power devices by P-type and I-type buried layers, in which the P-type buried layer is implanted into the P-substrate by silicon window underneath the source. The mechanism of breakdown is that the additional electric fields produced by P-type buried layer charges and different I-type buried layer modulate surface electric field, which...
In this paper, a novel silicon RF lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) structure, using an effective concept of dual-material gate (DMG), is proposed. The gate of the DMG-LDMOS consists of S-gate (the first gate approaching source with high workfunction material p+ poly) and D-gate (the second gate approaching drain with low workfunction material n+...
A simple one-dimensional (1-D) analytical method is proposed to analyze the breakdown properties of silicon-on-insulator (SOI) reduced surface field (RESURF) structure. Based on charge sharing concept, this approach transforms the inherent two-dimensional (2-D) effects into a simple 1-D equivalent depending on device parameters. It is first found that given the silicon thickness, the thicker buried...
The two structures of over 650V MR & MR SLMFFP double RESURF LDMOSs with HVI are experimentally realized using SPSM BCD process for high side gate drive IC. The experimental results, coincident with the three-dimensional simulations, show that the breakdown voltage of LDMOS will increase by reducing the width of HVI metal line. The breakdown voltages of the MR double RESURF LDMOS are 670V, 760V,...
A novel super-junction (SJ) LDMOS (SJ-LDMOS) with partial N-buried layer is proposed which allows high breakdown voltage (BV) and low on-resistance (Ron). The proposed structure overcomes the substrate-assisted-depletion effect thus achieving the charge compensation between the n and p pillars as well as a uniform electric field distribution in the drift region in the off-state. The N-buried layer...
For the low voltage power MOSFETs, the power loss and the switching frequency are the most important parameters, the two are separately determined by the conduction resistance RDS(on) and the gate charge QG. The gate charge mainly depends on the gate to drain charge QGD. The so-called figure-of-merit, which is defined as the product of the RDS(on) and QGD is commonly used to quantifying the performance...
X-ray and Co-60 irradiations caused large differences in charge buildup in SOI buried oxides because of the various electron-hole charge yield and dose enhancement effects. Dose enhancement effects are monitored with standard SOI NMOS transistors by measuring back-gate threshold shifts due to oxide-trapped charge. We have demonstrated that the device response to X-ray radiation can be used to predict...
A new method is proposed that uses a combined approach of inputs state assignment and clock signal assignment for idle footed dual Vt dominos at two typical die temperatures in nanometer CMOS technologies. Simulations based on 45nm BSIM4 models show that the previously CHIH state (the clock signal and inputs are all high) is only effective to suppress the leakage current of footed dual Vt dominos...
This brief investigates the influence of source and drain junction depth on the short-channel effect (SCE) in highly scaled MOSFETs. It is shown using two-dimensional finite-element device simulation that the influence of source and drain junction depth on SCE can be represented by an additional of a pre-exponential term to the established scale-length model. For source and drain junction depths that...
Excimer laser annealing (ELA) amorphous silicon (a-Si) to poly-silicon (poly-Si) in different gas environment, i.e. N2 or N2 mixed O2:2%, is studied for the fabrication of thin film transistors (TFTs). Influence of laser power on the surface morphology, grain size and height of gibbous grain is investigated. The variation of threshold laser power for the generation of surface ablation in N2 and N2...
In this paper, a novel structure of non-planar inductor based on silicon is presented. The simulation plot of the magnetic distribution reveals that magnetic field reaches its maximum intensity near the inner turns of planar inductor, so it is necessary to deal with the peak value of the magnetic field in the centre of the inductor which causes great substrate loss. An extra layer of silicon dioxide...
Thin film bulk acoustic resonators (FBAR) can be integrated in RFIC as an excellent RF and MF filter. Aimed at high frequency precision FBAR, a new method of evaporating the electrode layer of FBAR by laser is provided to trim FBAR resonant frequency. The experiment results confirm the feasibility of this method and show with a trimming precision up to 0.06%. Obvious frequency float was not detected...
In this study, a monolithic optoelectronic integrated circuit (OEIC), in which a photodiode detector and a bipolar integrated circuit for reception and amplification are integrated on the same silicon substrate, is described. With the new process technology, the layout of optical and electronic devices is designed, and the processes of optical and electronic devices are run. Thus a good way of developing...
A silicon optical emitter, including a light emitting device (LED) and a LED driver circuit, was realized in a standard 0.35mum CMOS technology. The LED operates in reverse breakdown mode and can be turned on at 8.3V. An output optical power of 13.6 nW was measured at 10V and 100mA, and the calculated emitted intensity was more than 1 mW/cm2 . The optical spectrum of the silicon LED is between 500-820nm...
In this paper a novel merged PiN Schottky rectifier structure based on semi-super junction technique, which is the combination of super junction (SJ) structure and n-bottom assisted layer (BAL), is proposed and demonstrated for a power-switching device. Optimal diode design is obtained exploiting a two dimension analytical model. Devices such as the blocking characteristic, the forward voltage-drop...
The zero-level stability, reliability and as well as the reproducibility of magnetic Hall sensors can be drastically spoiled by the offset voltage and its production spread. However, all these negative factors could be reduced using a single Hall plate and chopper stabilized amplifier stage which contains switching means for periodic permutation of the supply and output contact pairs. The present...
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