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In this paper, we discuss the physical principles of set of new measurement techniques to explore the reliability limits of (time dependent) dielectric breakdown (TDDB) and negative bias temperature instability (NBTI), two major reliability concerns of high performance logic/memory transistors. Our analysis of the techniques provides a sound theoretical foundation of the measurement algorithms. This...
The effect of gate-oxide reliability in MOSFET on common-source amplifiers is investigated with the non-stacked and stacked structures in a 130-nm low-voltage CMOS process. The supply voltage of 2.5 V is applied on the amplifiers to accelerate and observe the impact of gate-oxide reliability on circuit performances including small-signal gain, unity-gain frequency, and output DC voltage level under...
This paper presents reliability investigations in NLDEMOS transistor in 0.13μm SOI CMOS technology. Reliability tests under hot carrier injections (HCI) for different gate-lengths show two different degradation mechanisms. The modification of current path with short overlap (Olap) due to oblique equi-potential lines and the increase in the vertical electrical field under the gate edge at low V g lead...
Semiconductor optical amplifiers (SOAs) appear as key components for many applications for future optical networks and telecommunication systems due to various technological schemes that can be selected according to the targeted functions and performances (Eliseev, 1995). New qualification methodologies are now proposed to face the optoelectronic industry modifications and provide end-users with relevant...
In this paper, we demonstrate a practical alternative to the conventional SIL, which overcomes the above limitations. We show that it is possible to fabricate a lens directly on the back side of the silicon of the device under test. This lens works on principles of diffractive optics and is around 250 nm thick. The lens may be fabricated in about 1 hour, using a combination of FIB ion implantation...
During the development and qualification of a 300mm low-k/Cu back end of line (BEOL) technology, the long-term reliability of such interconnects including low-k time-dependent dielectric breakdown (TDDB), Cu electromigration (EM), Cu stress migration (SM), and Cu/low-k thermal behavior are rapidly becoming one of the most critical challenges. In this paper, a comprehensive reliability evaluation for...
In this paper, inter layer dielectric characteristic ramped voltage breakdown (VBD) performance of multiplayer Cu/SiOC interconnect was studied. The results showed that the breakdown reliability is highly process-related. Some dominating factors, such as via etching process, integration scheme used and Cu/dielectric interface etc., were discussed and proposed to improve breakdown reliability performance
In this paper, we demonstrate for the first time via technology computer aided design (TCAD), the enhancement in both the ac and dc performances for process-induced strained-Si MOSFETs over bulk-Si and a comparison of process-induced strained and substrate-induced strained-Si MOSFETs. In addition, we present the hot-electron degradation characteristics for strained-Si n-MOSFETs fabricated in both...
Electrical and SEM analysis of gate-silicided (GS) and gate-non-silicided (GNS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism switches away from classical drain-to-source filamentation when the silicidation between the silicide-blocked drain/source and the polysilicon gate is avoided. For 2.5V thick oxide devices, drain-to-substrate junction shorting was observed, whereas,...
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