The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a new Fast-Lock synthesizer for the recent GSM evolution GPRS, HSCSD and EDGE. The concept provides half the lock-in time of a common integer-N PLL with state-of-the-art phase noise and improved spurious suppression. Measurements of a high integrated GSM transceiver using the Fast-Lock concept show a sufficient lock-in time for the new standards. The PLL functional block can easily...
A Laser Driver IC for 10 Gb/s --SONET OC-192-- fiber optic transmitters is described. Depending on the user application, the IC is capable of driving up to 120 mA of current into a laser diode or 60 mA into an electro-absorption or Mach-Zehnder modulator with rise and fall times below 25 pS. In both cases the driver provides a DC-coupled back termination of either 25 or 50 Ω, implemented by means...
A 2 GHz fractional-N frequency synthesizer for telecommunications applications is presented. The synthesizer includes a multiple-modulus CMOS prescaler capable of operating at input frequencies of up to 2.15 GHz with a power dissipation of 12.5 mW, a third-order MASH ΔΣ-modulator that controls the modulus of the prescaler, and a phase detector and chargepump that doesn't suffer from dead-zone problems...
This paper introduces an analog phase and gain calibration technique for image-reject receivers. The technique uniquely detects the phase and gain mismatches and drives their magnitudes toward zero through the use of a negative-feedback loop. An experimental CMOS prototype operating at 900 MHz achieves an image rejection ratio of 57 dB by applying phase calibration to a Weaver architecture. Fabricated...
This paper presents a methodology that systematically generates wide-band CMOS Low Noise Amplifiers (LNAs), assuming that MOSFETs are exploited as a Voltage Controlled Current Source (VCCS). Using graph theory, ALL 2-VCCS LNAs are generated, and subsequently implemented using 2 NMOS transistors. Next to well-known circuits, two new wide-band LNAs are found. The most promising has been realized using...
This paper presents a 2V, full CMOS transmitter circuit to be included in a DCS-1800 wireless system. The paper discusses the design plan of the transmitter including the optimized interface with the differential oscillator, the poly-phase filter, the mixers and the preamplifying output driver. Traditional inter-building block buffers have been questioned, resulting in a transistor level optimization...
A 900-MHz CMOS Ultra-Low Noise Amplifier (LNA) has been integrated in a 0.35µm RF CMOS process with on-chip inductors. The LNA, housed in a standard TQFP48 package, features: Noise Figure NF=0.9dB with S11=-10.1dB, S22=-27dB, Power Gain Gp=14dB, input IP3=0dBm at Pdc=18mW. A NF=1.05dB is measured at Pdc=9mW. The reported LNA exhibits the best noise or power performance ever reported in CMOS technology.
This paper describes a 2-GHz single-chip 0.25-µm CMOS receiver for WCDMA applications. The receiver is based on a direct-conversion architecture and implements all RF components, including the low-noise amplifier, frequency synthesizer, and mixers. The receiver also integrates all baseband components along the in-phase and quadrature signal paths, each of which includes a first-order high-pass filter,...
A 700 MHz fully differential Class E CMOS power amplifier for wireless applications has been built. The prototype can deliver one Watt of output power in a 50Ω output impedance. The maximum power added efficiency (PAE) is measured to be 62%.
A new SHF RC I/Q oscillator architecture is presented which is derived from a two-integrator architecture. By using active inductive loads, a high maximum operating frequency is achieved. Automated circuit optimization shows that a maximum oscillation frequency of 20 GHz can be achieved in a 30 GHz ftprocess. The presented I/Q RC architecture is implemented in a 30 GHz ftBiCMOS process. The Carrier...
A BiCMOS replicating current comparator for use in analogue convolutional decoders is described. The circuit operates asynchronously by means of a negative feedback mechanism that provides an accurate virtual ground for current summation and comparison. Measurements showed that the comparator operates in excess of 200MHz, features a wide dynamic range, and consumes 5.8mW from a 2.8V power supply....
This paper presents the development of a full custom low power, mixed-mode, analog digital front-end chip for audio applications. The front-end is used with a full custom DSP ASIC in a high performance hearing aid system. The front-end implements functions as preamps, low power stereo audio analog to digital converters, remote-control receiver, high PSSR power supplies, time base, voltage reference...
A new high-speed and low-swing on-chip bus interface using Threshold Voltage swing (Vt) driver and Dual Sense Amplifier (DSA) receiver is proposed. The Vt-driver reduces the rising time in the bus to 30% of the full CMOS inverter and the DSA-receiver increases twice the throughput of the conventional reduced-swing buses using sense amplifiers. With Vt-driver and DSA-receiver combined, approximately...
We report an approach to improve the noise performance of RF low noise amplifiers (LNAs) and down-conversion mixers. The technique we described here is based on capacitive cross-coupling across the two sides of a differential input stage. A LNA and mixer have been implemented in 0.5µ CMOS process to demonstrate the viability of this technique. The measurements show that the LNA achieves 3.0dB noise...
A new logic family, Race Logic, is proposed for high speed and low power applications. Race Logic does not use transistors but utilise timing difference between two racing signals to implement boolean logic operations. Because the number of transistors is very small compared to conventional logic styles, delay time from clock to output is very small and the power consumption is also minimized. Various...
A 2.5-GHz/900-MHz dual fractional-N/integer-N frequency synthesizer is implemented in 0.35-µm, 25-GHz BiCMOS. A ΔΣ fractional-N synthesizer is employed for RF channels to have agile switching, low in-band noise and fine resolution. An on-chip voltage regulator is designed to reduce digital power and substrate noise. The in-band noise of -82 dBc/Hz with 35-kHz loop bandwidth is achieved at 2.47 GHz...
This paper presents a 500 kBit/s modem for space applications, designed for interfacing the satellite equipment with the On-Board Data Handling (OBDH) bus system. The 28 mm2chip, fabricated in a 0.8 µm SOI radiation-hard CMOS process, achieves a bit-error rate as low as 10-14with 120 mVRMSof noise consuming 64 mW from a 5 V power supply.
This paper relies on the design of an high-performance Track-and-Hold, intended to be used in data converters for telecommunication applications. Because of the challenging performance requirements an advanced SiGe bi-polar technology (fT= 75 GHz) has been used to implement the circuit. T&H measurements show a third harmonic better than -87 dBFS with a 1 Vpp,diffinput level, 110 MHz - 1 kHz signal...
This paper presents a burst-mode 155 Mb/s transmitter suitable for use in PON applications. It allows the transmitted optical power to be carefully controlled (<±5 %) over a wide temperature range (-40° to +80°). Moreover, it can be digitally programmed to work with a number of commercial lasers and to operate in Continuous-Wave transmission (at 155 Mb/s and 622 Mb/s). The chip was implemented...
A 12 GHz divide-by-128 frequency divider has been implemented in a first generation 0.25µm CMOS technology. High-speed divide-by-two flipflops have been developed, that are not only optimised for high frequency operation but also for driving the cascade of flipflops that form the divide-by-128 divider. An operating frequency of 12 GHz is achieved with a power consumption of 60 mW. In divide-by-16...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.