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This paper presents a new Fast-Lock synthesizer for the recent GSM evolution GPRS, HSCSD and EDGE. The concept provides half the lock-in time of a common integer-N PLL with state-of-the-art phase noise and improved spurious suppression. Measurements of a high integrated GSM transceiver using the Fast-Lock concept show a sufficient lock-in time for the new standards. The PLL functional block can easily...
A new 4-bit microcomputer, fabricated in a low power silicon gate CMOS process working on a supply voltage down to 1.2 V will be described. An operating power of 100 μW at 1.5 V make the chip ideal for control and timing applications in battery operated systems.
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