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Directory-based protocols are currently the method of choice to enforce cache coherence in large-scale shared-memory multiprocessors. The problems associated with these hardware schemes include their lack of scalability, although various suggestions have been made to ameliorate this drawback, and the loss of performance due to false sharing. Software controlled cache coherence (SCCC) is an alternative...
This paper presents a new fast way to simulate large networks of computers. The method uses a frontend EC, which accepts a parallel C program and translates it into a program in an intermediate language for parallel system simulations. An event driven simulator for distributed shared memory systems, DSIM, uses the intermediate language to simulate and obtain efficiency results in networks of thousands...
Fast computer simulation is an essential tool in the design of large parallel computers. We discuss the design and performance of our Fast Accurate Simulation Tool, FAST. We start by summarizing the tradeoffs made in the designs of this and other simulators. The key ideas used in this simulator involve execution driven simulation techniques that modify the object code of the application program being...
Shared memory architectures often have caches to reduce the number of slow remote memory accesses. The largest possible caches exist in shared memory architectures called Cache-Only Memory Architectures (COMAs). In a COMA all the memory resources are used to implement large caches. Unfortunately, these large caches also have their price. Due to its lack of physically shared memory, COMA may suffer...
Compares the performance, in shared-memory multiprocessors, of locating translation-lookaside buffers (TLBs) at processors with that of locating TLBs at memory. The comparison is based on trace-driven simulations of multiprocessors with log N-stage networks interconnecting N processors and N memory modules. For the systems and workloads studied, memory-based TLBs perform noticeably better than processor-based...
Synchronization and remote memory access delays cause staggering inefficiency in most shared memory programs if run on thousands of processors. The authors introduce efficient lock synchronization using the combination of group write consistency, which guarantees write ordering within groups of processors, and eagersharing distributed memory, which sends newly written data values over fast network...
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